diff --git a/gcc44-ix86-insn-length.patch b/gcc44-ix86-insn-length.patch
index 487f684..56490c8 100644
--- a/gcc44-ix86-insn-length.patch
+++ b/gcc44-ix86-insn-length.patch
@@ -359,6 +359,49 @@
  }
  
  #ifdef HAVE_ATTR_length
+--- gcc/config/i386/i386.h.jj	2009-06-09 17:54:57.000000000 +0200
++++ gcc/config/i386/i386.h	2009-06-09 11:20:00.000000000 +0200
+@@ -2209,6 +2210,22 @@ do {									\
+ #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+   ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
+ 
++/* A C statement to output to the stdio stream FILE an assembler
++   command to pad the location counter to a multiple of 1<<LOG
++   bytes if it is within MAX_SKIP bytes.  */
++
++#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
++#undef  ASM_OUTPUT_MAX_SKIP_PAD
++#define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP)			\
++  if ((LOG) != 0)							\
++    {									\
++      if ((MAX_SKIP) == 0)						\
++        fprintf ((FILE), "\t.p2align %d\n", (LOG));			\
++      else								\
++        fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP));	\
++    }
++#endif
++
+ /* Under some conditions we need jump tables in the text section,
+    because the assembler cannot handle label differences between
+    sections.  This is the case for x86_64 on Mach-O for example.  */
+--- gcc/config/i386/x86-64.h	(revision 147670)
++++ gcc/config/i386/x86-64.h	(revision 147671)
+@@ -81,6 +81,15 @@ see the files COPYING3 and COPYING.RUNTI
+       }									\
+     }									\
+   } while (0)
++#undef  ASM_OUTPUT_MAX_SKIP_PAD
++#define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP)			\
++  if ((LOG) != 0)							\
++    {									\
++      if ((MAX_SKIP) == 0)						\
++        fprintf ((FILE), "\t.p2align %d\n", (LOG));			\
++      else								\
++        fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP));	\
++    }
+ #endif
+ 
+ 
 --- gcc/config/i386/i386.c.jj	2009-06-09 10:24:35.000000000 +0200
 +++ gcc/config/i386/i386.c	2009-06-09 12:10:01.000000000 +0200
 @@ -8884,6 +8884,10 @@ ix86_decompose_address (rtx addr, struct
@@ -4611,6 +4654,27 @@
     (set_attr "atom_unit" "jeu")
     (set_attr "length_immediate" "0")
     (set_attr "prefix_rep" "1")
+@@ -15317,16 +15682,16 @@ (define_insn "nop"
+    (set_attr "length_immediate" "0")
+    (set_attr "modrm" "0")])
+ 
+-;; Align to 16-byte boundary, max skip in op0.  Used to avoid
++;; Pad to 16-byte boundary, max skip in op0.  Used to avoid
+ ;; branch prediction penalty for the third jump in a 16-byte
+ ;; block on K8.
+ 
+-(define_insn "align"
++(define_insn "pad"
+   [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
+   ""
+ {
+-#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
+-  ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
++#ifdef ASM_OUTPUT_MAX_SKIP_PAD
++  ASM_OUTPUT_MAX_SKIP_PAD (asm_out_file, 4, (int)INTVAL (operands[0]));
+ #else
+   /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
+      The align insn is used to avoid 3 jump instructions in the row to improve
 @@ -15367,7 +15732,8 @@ (define_insn "set_got_rex64"
    "TARGET_64BIT"
    "lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
diff --git a/gcc44-power7.patch b/gcc44-power7.patch
index e4078de..2f00006 100644
--- a/gcc44-power7.patch
+++ b/gcc44-power7.patch
@@ -3434,7 +3434,7 @@
 +  "du2_power7,VSU_power7")
 --- gcc/config/rs6000/rs6000-c.c	(.../trunk)	(revision 145777)
 +++ gcc/config/rs6000/rs6000-c.c	(.../branches/ibm/power7-meissner)	(revision 146027)
-@@ -105,11 +105,14 @@ altivec_categorize_keyword (const cpp_to
+@@ -106,14 +106,17 @@ altivec_categorize_keyword (const cpp_to
        if (ident == C_CPP_HASHNODE (vector_keyword))
  	return C_CPP_HASHNODE (__vector_keyword);
  
@@ -3449,11 +3449,16 @@
 -	return C_CPP_HASHNODE (__bool_keyword);
 +	  if (ident == C_CPP_HASHNODE (bool_keyword))
 +	    return C_CPP_HASHNODE (__bool_keyword);
+ 
+-      if (ident == C_CPP_HASHNODE (_Bool_keyword))
+-	return C_CPP_HASHNODE (__bool_keyword);
++	  if (ident == C_CPP_HASHNODE (_Bool_keyword))
++	    return C_CPP_HASHNODE (__bool_keyword);
 +	}
  
        return ident;
      }
-@@ -127,20 +130,23 @@ init_vector_keywords (void)
+@@ -131,23 +134,26 @@ init_vector_keywords (void)
    __vector_keyword = get_identifier ("__vector");
    C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
  
@@ -3475,19 +3480,24 @@
 +
 +      __bool_keyword = get_identifier ("__bool");
 +      C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL;
-+
-+      pixel_keyword = get_identifier ("pixel");
-+      C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
  
 -  bool_keyword = get_identifier ("bool");
 -  C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
++      pixel_keyword = get_identifier ("pixel");
++      C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
+ 
+-  _Bool_keyword = get_identifier ("_Bool");
+-  C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
 +      bool_keyword = get_identifier ("bool");
 +      C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
++
++      _Bool_keyword = get_identifier ("_Bool");
++      C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
 +    }
  }
  
  /* Called to decide whether a conditional macro should be expanded.
-@@ -207,7 +213,8 @@ rs6000_macro_to_expand (cpp_reader *pfil
+@@ -214,7 +220,8 @@ rs6000_macro_to_expand (cpp_reader *pfil
  	  if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
  	      || rid_code == RID_SHORT || rid_code == RID_SIGNED
  	      || rid_code == RID_INT || rid_code == RID_CHAR
@@ -3497,7 +3507,7 @@
  	    {
  	      expand_this = C_CPP_HASHNODE (__vector_keyword);
  	      /* If the next keyword is bool or pixel, it
-@@ -277,13 +284,14 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi
+@@ -284,13 +291,14 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi
      builtin_define ("_ARCH_PWR6X");
    if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC)
      builtin_define ("_ARCH_COM");
@@ -3513,13 +3523,16 @@
        builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
        builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned");
  
-@@ -292,9 +300,18 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi
+@@ -298,11 +306,20 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi
+ 	{
  	  /* Define this when supporting context-sensitive keywords.  */
  	  builtin_define ("__APPLE_ALTIVEC__");
- 	  
+-	  
 -	  builtin_define ("vector=vector");
++
  	  builtin_define ("pixel=pixel");
  	  builtin_define ("bool=bool");
+ 	  builtin_define ("_Bool=_Bool");
 +	}
 +    }
 +  if (TARGET_ALTIVEC || TARGET_VSX)
@@ -3533,7 +3546,7 @@
  	  init_vector_keywords ();
  
  	  /* Enable context-sensitive macros.  */
-@@ -318,6 +335,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi
+@@ -326,6 +343,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi
    /* Used by libstdc++.  */
    if (TARGET_NO_LWSYNC)
      builtin_define ("__NO_LWSYNC__");
@@ -3542,7 +3555,7 @@
  
    /* May be overridden by target configuration.  */
    RS6000_CPU_CPP_ENDIAN_BUILTINS();
-@@ -496,6 +515,8 @@ const struct altivec_builtin_types altiv
+@@ -504,6 +523,8 @@ const struct altivec_builtin_types altiv
      RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
@@ -3551,7 +3564,7 @@
    { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
-@@ -639,6 +660,12 @@ const struct altivec_builtin_types altiv
+@@ -647,6 +668,12 @@ const struct altivec_builtin_types altiv
    { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
      RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
@@ -3564,7 +3577,7 @@
      RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
      RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -687,6 +714,12 @@ const struct altivec_builtin_types altiv
+@@ -695,6 +722,12 @@ const struct altivec_builtin_types altiv
    { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
      RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
@@ -3577,7 +3590,7 @@
      RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
      RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -1190,6 +1223,8 @@ const struct altivec_builtin_types altiv
+@@ -1198,6 +1231,8 @@ const struct altivec_builtin_types altiv
      RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
@@ -3586,7 +3599,7 @@
    { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
-@@ -1366,6 +1401,8 @@ const struct altivec_builtin_types altiv
+@@ -1374,6 +1409,8 @@ const struct altivec_builtin_types altiv
      RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
@@ -3595,7 +3608,7 @@
    { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
-@@ -1451,6 +1488,8 @@ const struct altivec_builtin_types altiv
+@@ -1459,6 +1496,8 @@ const struct altivec_builtin_types altiv
    { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
@@ -3604,7 +3617,7 @@
      RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
      RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-@@ -1475,6 +1514,12 @@ const struct altivec_builtin_types altiv
+@@ -1483,6 +1522,12 @@ const struct altivec_builtin_types altiv
    { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
      RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
@@ -3617,7 +3630,7 @@
      RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
      RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -1932,6 +1977,8 @@ const struct altivec_builtin_types altiv
+@@ -1940,6 +1985,8 @@ const struct altivec_builtin_types altiv
      RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
@@ -3626,7 +3639,7 @@
    { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
      RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
-@@ -2091,6 +2138,12 @@ const struct altivec_builtin_types altiv
+@@ -2099,6 +2146,12 @@ const struct altivec_builtin_types altiv
    { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
      RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
    { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
@@ -3639,7 +3652,7 @@
      RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
    { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
      RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
-@@ -2981,8 +3034,10 @@ altivec_resolve_overloaded_builtin (tree
+@@ -2989,8 +3042,10 @@ altivec_resolve_overloaded_builtin (tree
    const struct altivec_builtin_types *desc;
    int n;