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From patchwork Mon Mar  6 17:17:45 2017
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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Subject: [v8, 1/6] ARM: dts: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI
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From: Icenowy Zheng <icenowy@aosc.xyz>
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X-Patchwork-Id: 9607205
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Message-Id: <20170306171750.7491-2-icenowy@aosc.xyz>
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To: Rob Herring <robh+dt@kernel.org>,
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 Maxime Ripard <maxime.ripard@free-electrons.com>,
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 Chen-Yu Tsai <wens@csie.org>
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Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,
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 linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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 Icenowy Zheng <icenowy@aosc.xyz>
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Date: Tue,  7 Mar 2017 01:17:45 +0800
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The skeleton.dtsi file is now deprecated, and do not exist in ARM64
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environment.
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Since we will soon reuse most part of H3 DTSI for H5, which is an ARM64
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chip, drop skeleton.dtsi inclusion now.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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---
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Changes in v8:
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- Add h3: in commit message.
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 arch/arm/boot/dts/sun8i-h3.dtsi | 2 --
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 1 file changed, 2 deletions(-)
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diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
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index 27780b97c863..9a3435527fde 100644
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -40,8 +40,6 @@
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  *     OTHER DEALINGS IN THE SOFTWARE.
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  */
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-#include "skeleton.dtsi"
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-
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 #include <dt-bindings/clock/sun8i-h3-ccu.h>
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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 #include <dt-bindings/pinctrl/sun4i-a10.h>
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From patchwork Mon Mar  6 17:17:46 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v8,
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 2/6] ARM: dts: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
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From: Icenowy Zheng <icenowy@aosc.xyz>
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X-Patchwork-Id: 9607207
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Message-Id: <20170306171750.7491-3-icenowy@aosc.xyz>
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To: Rob Herring <robh+dt@kernel.org>,
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 Maxime Ripard <maxime.ripard@free-electrons.com>,
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 Chen-Yu Tsai <wens@csie.org>
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Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,
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 linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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 Icenowy Zheng <icenowy@aosc.xyz>
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Date: Tue,  7 Mar 2017 01:17:46 +0800
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After converting to generic pinconf binding, pinctrl-a10.h is now not
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used at all.
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Drop its inclusion for H3 DTSI.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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---
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Changes in v8:
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- Add h3: in commit message.
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 arch/arm/boot/dts/sun8i-h3.dtsi | 1 -
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 1 file changed, 1 deletion(-)
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diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
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index 9a3435527fde..b250e6d03b57 100644
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -42,7 +42,6 @@
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 #include <dt-bindings/clock/sun8i-h3-ccu.h>
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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-#include <dt-bindings/pinctrl/sun4i-a10.h>
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 #include <dt-bindings/reset/sun8i-h3-ccu.h>
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 / {
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From patchwork Mon Mar  6 17:17:47 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v8,
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 3/6] ARM: dts: sun8i: h3: correct the GIC compatible in H3 to gic-400
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From: Icenowy Zheng <icenowy@aosc.xyz>
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X-Patchwork-Id: 9607209
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Message-Id: <20170306171750.7491-4-icenowy@aosc.xyz>
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To: Rob Herring <robh+dt@kernel.org>,
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 Maxime Ripard <maxime.ripard@free-electrons.com>,
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 Chen-Yu Tsai <wens@csie.org>
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Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,
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 linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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 Icenowy Zheng <icenowy@aosc.xyz>
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Date: Tue,  7 Mar 2017 01:17:47 +0800
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According to the datasheets provided by Allwinner, both Allwinner H3 and
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H5 use GIC-400 as their interrupt controller.
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For better device tree reusing, correct the GIC compatible in H3 DTSI to
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"arm,gic-400", thus this node can be reused in H5.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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---
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Changes in v8:
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- Add h3: in commit message.
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 arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
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 1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
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index b250e6d03b57..c13fbfb92592 100644
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -586,7 +586,7 @@
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 		};
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 		gic: interrupt-controller@01c81000 {
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-			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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+			compatible = "arm,gic-400";
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 			reg = <0x01c81000 0x1000>,
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 			      <0x01c82000 0x2000>,
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 			      <0x01c84000 0x2000>,
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From patchwork Mon Mar  6 17:17:48 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v8,4/6] arm: dts: sun8i: h3: split Allwinner H3 .dtsi
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From: Icenowy Zheng <icenowy@aosc.xyz>
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X-Patchwork-Id: 9607211
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Message-Id: <20170306171750.7491-5-icenowy@aosc.xyz>
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To: Rob Herring <robh+dt@kernel.org>,
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 Maxime Ripard <maxime.ripard@free-electrons.com>,
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 Chen-Yu Tsai <wens@csie.org>
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Cc: devicetree@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>,
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 linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
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 Icenowy Zheng <icenowy@aosc.xyz>, linux-arm-kernel@lists.infradead.org
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Date: Tue,  7 Mar 2017 01:17:48 +0800
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From: Andre Przywara <andre.przywara@arm.com>
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The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the
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Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller
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updated. So we should really share almost the whole .dtsi.
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In preparation for that move the peripheral parts of the existing
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sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi.
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The actual sun8i-h3.dtsi then includes that and defines the H3 specific
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parts on top of it.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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[Icenowy: also split out mmc and gic, as well as pio and ccu's
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 compatible, and make drop of skeleton into a seperated patch]
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Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
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---
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Changes in v8:
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- Add h3: in commit message.
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Changes in v7:
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- Extract GIC, skeleton.dtsi and pinctrl-a10.h changes to seperate patches.
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Changes in v6:
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- Extract GIC device node to sunxi-h3-h5.dtsi and correct its compatible
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  as "arm,gic-400".
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Changes in v3:
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- Use label-based syntax to reference nodes in H3 DTSI file.
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Changes in v2:
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- Rebase on current linux-next (because of the add of audio codec)
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 arch/arm/boot/dts/sun8i-h3.dtsi                    | 771 ++++-----------------
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 .../boot/dts/{sun8i-h3.dtsi => sunxi-h3-h5.dtsi}   |  73 +-
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 2 files changed, 133 insertions(+), 711 deletions(-)
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 rewrite arch/arm/boot/dts/sun8i-h3.dtsi (83%)
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 copy arch/arm/boot/dts/{sun8i-h3.dtsi => sunxi-h3-h5.dtsi} (90%)
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diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
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dissimilarity index 83%
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index c13fbfb92592..b36f9f423c39 100644
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -1,645 +1,126 @@
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-/*
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- * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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- *
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- * This file is dual-licensed: you can use it either under the terms
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- * of the GPL or the X11 license, at your option. Note that this dual
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- * licensing only applies to this file, and not this project as a
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- * whole.
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- *
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- *  a) This file is free software; you can redistribute it and/or
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- *     modify it under the terms of the GNU General Public License as
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- *     published by the Free Software Foundation; either version 2 of the
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- *     License, or (at your option) any later version.
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- *
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- *     This file is distributed in the hope that it will be useful,
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- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
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- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- *     GNU General Public License for more details.
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- *
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- * Or, alternatively,
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- *
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- *  b) Permission is hereby granted, free of charge, to any person
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- *     obtaining a copy of this software and associated documentation
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- *     files (the "Software"), to deal in the Software without
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- *     restriction, including without limitation the rights to use,
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- *     copy, modify, merge, publish, distribute, sublicense, and/or
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- *     sell copies of the Software, and to permit persons to whom the
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- *     Software is furnished to do so, subject to the following
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- *     conditions:
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- *
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- *     The above copyright notice and this permission notice shall be
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- *     included in all copies or substantial portions of the Software.
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- *
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- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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- *     OTHER DEALINGS IN THE SOFTWARE.
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- */
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-
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-#include <dt-bindings/clock/sun8i-h3-ccu.h>
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-#include <dt-bindings/interrupt-controller/arm-gic.h>
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-#include <dt-bindings/reset/sun8i-h3-ccu.h>
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-
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-/ {
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-	interrupt-parent = <&gic;;
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-
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-	cpus {
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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-
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-		cpu@0 {
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-			compatible = "arm,cortex-a7";
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-			device_type = "cpu";
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-			reg = <0>;
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-		};
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-
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-		cpu@1 {
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-			compatible = "arm,cortex-a7";
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-			device_type = "cpu";
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-			reg = <1>;
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-		};
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-
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-		cpu@2 {
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-			compatible = "arm,cortex-a7";
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-			device_type = "cpu";
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-			reg = <2>;
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-		};
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-
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-		cpu@3 {
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-			compatible = "arm,cortex-a7";
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-			device_type = "cpu";
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-			reg = <3>;
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-		};
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-	};
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-
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-	timer {
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-		compatible = "arm,armv7-timer";
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-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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-	};
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-
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-	clocks {
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-		#address-cells = <1>;
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-		#size-cells = <1>;
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-		ranges;
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-
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-		osc24M: osc24M_clk {
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-			#clock-cells = <0>;
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-			compatible = "fixed-clock";
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-			clock-frequency = <24000000>;
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-			clock-output-names = "osc24M";
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-		};
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-
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-		osc32k: osc32k_clk {
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-			#clock-cells = <0>;
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-			compatible = "fixed-clock";
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-			clock-frequency = <32768>;
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-			clock-output-names = "osc32k";
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-		};
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-
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-		apb0: apb0_clk {
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-			compatible = "fixed-factor-clock";
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-			#clock-cells = <0>;
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-			clock-div = <1>;
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-			clock-mult = <1>;
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-			clocks = <&osc24M>;
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-			clock-output-names = "apb0";
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-		};
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-
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-		apb0_gates: clk@01f01428 {
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-			compatible = "allwinner,sun8i-h3-apb0-gates-clk",
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-				     "allwinner,sun4i-a10-gates-clk";
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-			reg = <0x01f01428 0x4>;
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-			#clock-cells = <1>;
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-			clocks = <&apb0>;
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-			clock-indices = <0>, <1>;
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-			clock-output-names = "apb0_pio", "apb0_ir";
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-		};
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-
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-		ir_clk: ir_clk@01f01454 {
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-			compatible = "allwinner,sun4i-a10-mod0-clk";
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-			reg = <0x01f01454 0x4>;
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-			#clock-cells = <0>;
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-			clocks = <&osc32k>, <&osc24M>;
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-			clock-output-names = "ir";
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-		};
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-	};
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-
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-	soc {
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-		compatible = "simple-bus";
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-		#address-cells = <1>;
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-		#size-cells = <1>;
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-		ranges;
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-
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-		dma: dma-controller@01c02000 {
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-			compatible = "allwinner,sun8i-h3-dma";
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-			reg = <0x01c02000 0x1000>;
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-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&ccu CLK_BUS_DMA>;
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-			resets = <&ccu RST_BUS_DMA>;
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-			#dma-cells = <1>;
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-		};
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-
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-		mmc0: mmc@01c0f000 {
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-			compatible = "allwinner,sun7i-a20-mmc";
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-			reg = <0x01c0f000 0x1000>;
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-			clocks = <&ccu CLK_BUS_MMC0>,
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-				 <&ccu CLK_MMC0>,
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-				 <&ccu CLK_MMC0_OUTPUT>,
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-				 <&ccu CLK_MMC0_SAMPLE>;
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-			clock-names = "ahb",
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-				      "mmc",
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-				      "output",
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-				      "sample";
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-			resets = <&ccu RST_BUS_MMC0>;
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-			reset-names = "ahb";
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-			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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-			status = "disabled";
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-			#address-cells = <1>;
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-			#size-cells = <0>;
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-		};
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-
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-		mmc1: mmc@01c10000 {
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-			compatible = "allwinner,sun7i-a20-mmc";
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-			reg = <0x01c10000 0x1000>;
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-			clocks = <&ccu CLK_BUS_MMC1>,
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-				 <&ccu CLK_MMC1>,
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-				 <&ccu CLK_MMC1_OUTPUT>,
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-				 <&ccu CLK_MMC1_SAMPLE>;
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-			clock-names = "ahb",
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-				      "mmc",
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-				      "output",
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-				      "sample";
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-			resets = <&ccu RST_BUS_MMC1>;
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-			reset-names = "ahb";
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-			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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-			status = "disabled";
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-			#address-cells = <1>;
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-			#size-cells = <0>;
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-		};
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-
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-		mmc2: mmc@01c11000 {
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-			compatible = "allwinner,sun7i-a20-mmc";
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-			reg = <0x01c11000 0x1000>;
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-			clocks = <&ccu CLK_BUS_MMC2>,
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-				 <&ccu CLK_MMC2>,
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-				 <&ccu CLK_MMC2_OUTPUT>,
58a0e11
-				 <&ccu CLK_MMC2_SAMPLE>;
58a0e11
-			clock-names = "ahb",
58a0e11
-				      "mmc",
58a0e11
-				      "output",
58a0e11
-				      "sample";
58a0e11
-			resets = <&ccu RST_BUS_MMC2>;
58a0e11
-			reset-names = "ahb";
58a0e11
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			status = "disabled";
58a0e11
-			#address-cells = <1>;
58a0e11
-			#size-cells = <0>;
58a0e11
-		};
58a0e11
-
58a0e11
-		usbphy: phy@01c19400 {
58a0e11
-			compatible = "allwinner,sun8i-h3-usb-phy";
58a0e11
-			reg = <0x01c19400 0x2c>,
58a0e11
-			      <0x01c1a800 0x4>,
58a0e11
-			      <0x01c1b800 0x4>,
58a0e11
-			      <0x01c1c800 0x4>,
58a0e11
-			      <0x01c1d800 0x4>;
58a0e11
-			reg-names = "phy_ctrl",
58a0e11
-				    "pmu0",
58a0e11
-				    "pmu1",
58a0e11
-				    "pmu2",
58a0e11
-				    "pmu3";
58a0e11
-			clocks = <&ccu CLK_USB_PHY0>,
58a0e11
-				 <&ccu CLK_USB_PHY1>,
58a0e11
-				 <&ccu CLK_USB_PHY2>,
58a0e11
-				 <&ccu CLK_USB_PHY3>;
58a0e11
-			clock-names = "usb0_phy",
58a0e11
-				      "usb1_phy",
58a0e11
-				      "usb2_phy",
58a0e11
-				      "usb3_phy";
58a0e11
-			resets = <&ccu RST_USB_PHY0>,
58a0e11
-				 <&ccu RST_USB_PHY1>,
58a0e11
-				 <&ccu RST_USB_PHY2>,
58a0e11
-				 <&ccu RST_USB_PHY3>;
58a0e11
-			reset-names = "usb0_reset",
58a0e11
-				      "usb1_reset",
58a0e11
-				      "usb2_reset",
58a0e11
-				      "usb3_reset";
58a0e11
-			status = "disabled";
58a0e11
-			#phy-cells = <1>;
58a0e11
-		};
58a0e11
-
58a0e11
-		ehci1: usb@01c1b000 {
58a0e11
-			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
58a0e11
-			reg = <0x01c1b000 0x100>;
58a0e11
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
58a0e11
-			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
58a0e11
-			phys = <&usbphy 1>;
58a0e11
-			phy-names = "usb";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		ohci1: usb@01c1b400 {
58a0e11
-			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
58a0e11
-			reg = <0x01c1b400 0x100>;
58a0e11
-			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
58a0e11
-				 <&ccu CLK_USB_OHCI1>;
58a0e11
-			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
58a0e11
-			phys = <&usbphy 1>;
58a0e11
-			phy-names = "usb";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		ehci2: usb@01c1c000 {
58a0e11
-			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
58a0e11
-			reg = <0x01c1c000 0x100>;
58a0e11
-			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
58a0e11
-			resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
58a0e11
-			phys = <&usbphy 2>;
58a0e11
-			phy-names = "usb";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		ohci2: usb@01c1c400 {
58a0e11
-			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
58a0e11
-			reg = <0x01c1c400 0x100>;
58a0e11
-			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
58a0e11
-				 <&ccu CLK_USB_OHCI2>;
58a0e11
-			resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
58a0e11
-			phys = <&usbphy 2>;
58a0e11
-			phy-names = "usb";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		ehci3: usb@01c1d000 {
58a0e11
-			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
58a0e11
-			reg = <0x01c1d000 0x100>;
58a0e11
-			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
58a0e11
-			resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
58a0e11
-			phys = <&usbphy 3>;
58a0e11
-			phy-names = "usb";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		ohci3: usb@01c1d400 {
58a0e11
-			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
58a0e11
-			reg = <0x01c1d400 0x100>;
58a0e11
-			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
58a0e11
-				 <&ccu CLK_USB_OHCI3>;
58a0e11
-			resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
58a0e11
-			phys = <&usbphy 3>;
58a0e11
-			phy-names = "usb";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		ccu: clock@01c20000 {
58a0e11
-			compatible = "allwinner,sun8i-h3-ccu";
58a0e11
-			reg = <0x01c20000 0x400>;
58a0e11
-			clocks = <&osc24M>, <&osc32k>;
58a0e11
-			clock-names = "hosc", "losc";
58a0e11
-			#clock-cells = <1>;
58a0e11
-			#reset-cells = <1>;
58a0e11
-		};
58a0e11
-
58a0e11
-		pio: pinctrl@01c20800 {
58a0e11
-			compatible = "allwinner,sun8i-h3-pinctrl";
58a0e11
-			reg = <0x01c20800 0x400>;
58a0e11
-			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
58a0e11
-				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
58a0e11
-			clock-names = "apb", "hosc", "losc";
58a0e11
-			gpio-controller;
58a0e11
-			#gpio-cells = <3>;
58a0e11
-			interrupt-controller;
58a0e11
-			#interrupt-cells = <3>;
58a0e11
-
58a0e11
-			i2c0_pins: i2c0 {
58a0e11
-				pins = "PA11", "PA12";
58a0e11
-				function = "i2c0";
58a0e11
-			};
58a0e11
-
58a0e11
-			i2c1_pins: i2c1 {
58a0e11
-				pins = "PA18", "PA19";
58a0e11
-				function = "i2c1";
58a0e11
-			};
58a0e11
-
58a0e11
-			i2c2_pins: i2c2 {
58a0e11
-				pins = "PE12", "PE13";
58a0e11
-				function = "i2c2";
58a0e11
-			};
58a0e11
-
58a0e11
-			mmc0_pins_a: mmc0@0 {
58a0e11
-				pins = "PF0", "PF1", "PF2", "PF3",
58a0e11
-				       "PF4", "PF5";
58a0e11
-				function = "mmc0";
58a0e11
-				drive-strength = <30>;
58a0e11
-				bias-pull-up;
58a0e11
-			};
58a0e11
-
58a0e11
-			mmc0_cd_pin: mmc0_cd_pin@0 {
58a0e11
-				pins = "PF6";
58a0e11
-				function = "gpio_in";
58a0e11
-				bias-pull-up;
58a0e11
-			};
58a0e11
-
58a0e11
-			mmc1_pins_a: mmc1@0 {
58a0e11
-				pins = "PG0", "PG1", "PG2", "PG3",
58a0e11
-				       "PG4", "PG5";
58a0e11
-				function = "mmc1";
58a0e11
-				drive-strength = <30>;
58a0e11
-				bias-pull-up;
58a0e11
-			};
58a0e11
-
58a0e11
-			mmc2_8bit_pins: mmc2_8bit {
58a0e11
-				pins = "PC5", "PC6", "PC8",
58a0e11
-				       "PC9", "PC10", "PC11",
58a0e11
-				       "PC12", "PC13", "PC14",
58a0e11
-				       "PC15", "PC16";
58a0e11
-				function = "mmc2";
58a0e11
-				drive-strength = <30>;
58a0e11
-				bias-pull-up;
58a0e11
-			};
58a0e11
-
58a0e11
-			spdif_tx_pins_a: spdif@0 {
58a0e11
-				pins = "PA17";
58a0e11
-				function = "spdif";
58a0e11
-			};
58a0e11
-
58a0e11
-			spi0_pins: spi0 {
58a0e11
-				pins = "PC0", "PC1", "PC2", "PC3";
58a0e11
-				function = "spi0";
58a0e11
-			};
58a0e11
-
58a0e11
-			spi1_pins: spi1 {
58a0e11
-				pins = "PA15", "PA16", "PA14", "PA13";
58a0e11
-				function = "spi1";
58a0e11
-			};
58a0e11
-
58a0e11
-			uart0_pins_a: uart0@0 {
58a0e11
-				pins = "PA4", "PA5";
58a0e11
-				function = "uart0";
58a0e11
-			};
58a0e11
-
58a0e11
-			uart1_pins: uart1 {
58a0e11
-				pins = "PG6", "PG7";
58a0e11
-				function = "uart1";
58a0e11
-			};
58a0e11
-
58a0e11
-			uart1_rts_cts_pins: uart1_rts_cts {
58a0e11
-				pins = "PG8", "PG9";
58a0e11
-				function = "uart1";
58a0e11
-			};
58a0e11
-
58a0e11
-			uart2_pins: uart2 {
58a0e11
-				pins = "PA0", "PA1";
58a0e11
-				function = "uart2";
58a0e11
-			};
58a0e11
-
58a0e11
-			uart3_pins: uart3 {
58a0e11
-				pins = "PA13", "PA14";
58a0e11
-				function = "uart3";
58a0e11
-			};
58a0e11
-		};
58a0e11
-
58a0e11
-		timer@01c20c00 {
58a0e11
-			compatible = "allwinner,sun4i-a10-timer";
58a0e11
-			reg = <0x01c20c00 0xa0>;
58a0e11
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
58a0e11
-				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&osc24M>;
58a0e11
-		};
58a0e11
-
58a0e11
-		spi0: spi@01c68000 {
58a0e11
-			compatible = "allwinner,sun8i-h3-spi";
58a0e11
-			reg = <0x01c68000 0x1000>;
58a0e11
-			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
58a0e11
-			clock-names = "ahb", "mod";
58a0e11
-			dmas = <&dma 23>, <&dma 23>;
58a0e11
-			dma-names = "rx", "tx";
58a0e11
-			pinctrl-names = "default";
58a0e11
-			pinctrl-0 = <&spi0_pins>;
58a0e11
-			resets = <&ccu RST_BUS_SPI0>;
58a0e11
-			status = "disabled";
58a0e11
-			#address-cells = <1>;
58a0e11
-			#size-cells = <0>;
58a0e11
-		};
58a0e11
-
58a0e11
-		spi1: spi@01c69000 {
58a0e11
-			compatible = "allwinner,sun8i-h3-spi";
58a0e11
-			reg = <0x01c69000 0x1000>;
58a0e11
-			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
58a0e11
-			clock-names = "ahb", "mod";
58a0e11
-			dmas = <&dma 24>, <&dma 24>;
58a0e11
-			dma-names = "rx", "tx";
58a0e11
-			pinctrl-names = "default";
58a0e11
-			pinctrl-0 = <&spi1_pins>;
58a0e11
-			resets = <&ccu RST_BUS_SPI1>;
58a0e11
-			status = "disabled";
58a0e11
-			#address-cells = <1>;
58a0e11
-			#size-cells = <0>;
58a0e11
-		};
58a0e11
-
58a0e11
-		wdt0: watchdog@01c20ca0 {
58a0e11
-			compatible = "allwinner,sun6i-a31-wdt";
58a0e11
-			reg = <0x01c20ca0 0x20>;
58a0e11
-			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-		};
58a0e11
-
58a0e11
-		spdif: spdif@01c21000 {
58a0e11
-			#sound-dai-cells = <0>;
58a0e11
-			compatible = "allwinner,sun8i-h3-spdif";
58a0e11
-			reg = <0x01c21000 0x400>;
58a0e11
-			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
58a0e11
-			resets = <&ccu RST_BUS_SPDIF>;
58a0e11
-			clock-names = "apb", "spdif";
58a0e11
-			dmas = <&dma 2>;
58a0e11
-			dma-names = "tx";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		pwm: pwm@01c21400 {
58a0e11
-			compatible = "allwinner,sun8i-h3-pwm";
58a0e11
-			reg = <0x01c21400 0x8>;
58a0e11
-			clocks = <&osc24M>;
58a0e11
-			#pwm-cells = <3>;
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		codec: codec@01c22c00 {
58a0e11
-			#sound-dai-cells = <0>;
58a0e11
-			compatible = "allwinner,sun8i-h3-codec";
58a0e11
-			reg = <0x01c22c00 0x400>;
58a0e11
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
58a0e11
-			clock-names = "apb", "codec";
58a0e11
-			resets = <&ccu RST_BUS_CODEC>;
58a0e11
-			dmas = <&dma 15>, <&dma 15>;
58a0e11
-			dma-names = "rx", "tx";
58a0e11
-			allwinner,codec-analog-controls = <&codec_analog>;
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		uart0: serial@01c28000 {
58a0e11
-			compatible = "snps,dw-apb-uart";
58a0e11
-			reg = <0x01c28000 0x400>;
58a0e11
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			reg-shift = <2>;
58a0e11
-			reg-io-width = <4>;
58a0e11
-			clocks = <&ccu CLK_BUS_UART0>;
58a0e11
-			resets = <&ccu RST_BUS_UART0>;
58a0e11
-			dmas = <&dma 6>, <&dma 6>;
58a0e11
-			dma-names = "rx", "tx";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		uart1: serial@01c28400 {
58a0e11
-			compatible = "snps,dw-apb-uart";
58a0e11
-			reg = <0x01c28400 0x400>;
58a0e11
-			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			reg-shift = <2>;
58a0e11
-			reg-io-width = <4>;
58a0e11
-			clocks = <&ccu CLK_BUS_UART1>;
58a0e11
-			resets = <&ccu RST_BUS_UART1>;
58a0e11
-			dmas = <&dma 7>, <&dma 7>;
58a0e11
-			dma-names = "rx", "tx";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		uart2: serial@01c28800 {
58a0e11
-			compatible = "snps,dw-apb-uart";
58a0e11
-			reg = <0x01c28800 0x400>;
58a0e11
-			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			reg-shift = <2>;
58a0e11
-			reg-io-width = <4>;
58a0e11
-			clocks = <&ccu CLK_BUS_UART2>;
58a0e11
-			resets = <&ccu RST_BUS_UART2>;
58a0e11
-			dmas = <&dma 8>, <&dma 8>;
58a0e11
-			dma-names = "rx", "tx";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		uart3: serial@01c28c00 {
58a0e11
-			compatible = "snps,dw-apb-uart";
58a0e11
-			reg = <0x01c28c00 0x400>;
58a0e11
-			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			reg-shift = <2>;
58a0e11
-			reg-io-width = <4>;
58a0e11
-			clocks = <&ccu CLK_BUS_UART3>;
58a0e11
-			resets = <&ccu RST_BUS_UART3>;
58a0e11
-			dmas = <&dma 9>, <&dma 9>;
58a0e11
-			dma-names = "rx", "tx";
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		i2c0: i2c@01c2ac00 {
58a0e11
-			compatible = "allwinner,sun6i-a31-i2c";
58a0e11
-			reg = <0x01c2ac00 0x400>;
58a0e11
-			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_I2C0>;
58a0e11
-			resets = <&ccu RST_BUS_I2C0>;
58a0e11
-			pinctrl-names = "default";
58a0e11
-			pinctrl-0 = <&i2c0_pins>;
58a0e11
-			status = "disabled";
58a0e11
-			#address-cells = <1>;
58a0e11
-			#size-cells = <0>;
58a0e11
-		};
58a0e11
-
58a0e11
-		i2c1: i2c@01c2b000 {
58a0e11
-			compatible = "allwinner,sun6i-a31-i2c";
58a0e11
-			reg = <0x01c2b000 0x400>;
58a0e11
-			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_I2C1>;
58a0e11
-			resets = <&ccu RST_BUS_I2C1>;
58a0e11
-			pinctrl-names = "default";
58a0e11
-			pinctrl-0 = <&i2c1_pins>;
58a0e11
-			status = "disabled";
58a0e11
-			#address-cells = <1>;
58a0e11
-			#size-cells = <0>;
58a0e11
-		};
58a0e11
-
58a0e11
-		i2c2: i2c@01c2b400 {
58a0e11
-			compatible = "allwinner,sun6i-a31-i2c";
58a0e11
-			reg = <0x01c2b000 0x400>;
58a0e11
-			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&ccu CLK_BUS_I2C2>;
58a0e11
-			resets = <&ccu RST_BUS_I2C2>;
58a0e11
-			pinctrl-names = "default";
58a0e11
-			pinctrl-0 = <&i2c2_pins>;
58a0e11
-			status = "disabled";
58a0e11
-			#address-cells = <1>;
58a0e11
-			#size-cells = <0>;
58a0e11
-		};
58a0e11
-
58a0e11
-		gic: interrupt-controller@01c81000 {
58a0e11
-			compatible = "arm,gic-400";
58a0e11
-			reg = <0x01c81000 0x1000>,
58a0e11
-			      <0x01c82000 0x2000>,
58a0e11
-			      <0x01c84000 0x2000>,
58a0e11
-			      <0x01c86000 0x2000>;
58a0e11
-			interrupt-controller;
58a0e11
-			#interrupt-cells = <3>;
58a0e11
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
58a0e11
-		};
58a0e11
-
58a0e11
-		rtc: rtc@01f00000 {
58a0e11
-			compatible = "allwinner,sun6i-a31-rtc";
58a0e11
-			reg = <0x01f00000 0x54>;
58a0e11
-			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
58a0e11
-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-		};
58a0e11
-
58a0e11
-		apb0_reset: reset@01f014b0 {
58a0e11
-			reg = <0x01f014b0 0x4>;
58a0e11
-			compatible = "allwinner,sun6i-a31-clock-reset";
58a0e11
-			#reset-cells = <1>;
58a0e11
-		};
58a0e11
-
58a0e11
-		codec_analog: codec-analog@01f015c0 {
58a0e11
-			compatible = "allwinner,sun8i-h3-codec-analog";
58a0e11
-			reg = <0x01f015c0 0x4>;
58a0e11
-		};
58a0e11
-
58a0e11
-		ir: ir@01f02000 {
58a0e11
-			compatible = "allwinner,sun5i-a13-ir";
58a0e11
-			clocks = <&apb0_gates 1>, <&ir_clk>;
58a0e11
-			clock-names = "apb", "ir";
58a0e11
-			resets = <&apb0_reset 1>;
58a0e11
-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			reg = <0x01f02000 0x40>;
58a0e11
-			status = "disabled";
58a0e11
-		};
58a0e11
-
58a0e11
-		r_pio: pinctrl@01f02c00 {
58a0e11
-			compatible = "allwinner,sun8i-h3-r-pinctrl";
58a0e11
-			reg = <0x01f02c00 0x400>;
58a0e11
-			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
-			clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
58a0e11
-			clock-names = "apb", "hosc", "losc";
58a0e11
-			resets = <&apb0_reset 0>;
58a0e11
-			gpio-controller;
58a0e11
-			#gpio-cells = <3>;
58a0e11
-			interrupt-controller;
58a0e11
-			#interrupt-cells = <3>;
58a0e11
-
58a0e11
-			ir_pins_a: ir@0 {
58a0e11
-				pins = "PL11";
58a0e11
-				function = "s_cir_rx";
58a0e11
-			};
58a0e11
-		};
58a0e11
-	};
58a0e11
-};
58a0e11
+/*
58a0e11
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
58a0e11
+ *
58a0e11
+ * This file is dual-licensed: you can use it either under the terms
58a0e11
+ * of the GPL or the X11 license, at your option. Note that this dual
58a0e11
+ * licensing only applies to this file, and not this project as a
58a0e11
+ * whole.
58a0e11
+ *
58a0e11
+ *  a) This file is free software; you can redistribute it and/or
58a0e11
+ *     modify it under the terms of the GNU General Public License as
58a0e11
+ *     published by the Free Software Foundation; either version 2 of the
58a0e11
+ *     License, or (at your option) any later version.
58a0e11
+ *
58a0e11
+ *     This file is distributed in the hope that it will be useful,
58a0e11
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
58a0e11
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
58a0e11
+ *     GNU General Public License for more details.
58a0e11
+ *
58a0e11
+ * Or, alternatively,
58a0e11
+ *
58a0e11
+ *  b) Permission is hereby granted, free of charge, to any person
58a0e11
+ *     obtaining a copy of this software and associated documentation
58a0e11
+ *     files (the "Software"), to deal in the Software without
58a0e11
+ *     restriction, including without limitation the rights to use,
58a0e11
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
58a0e11
+ *     sell copies of the Software, and to permit persons to whom the
58a0e11
+ *     Software is furnished to do so, subject to the following
58a0e11
+ *     conditions:
58a0e11
+ *
58a0e11
+ *     The above copyright notice and this permission notice shall be
58a0e11
+ *     included in all copies or substantial portions of the Software.
58a0e11
+ *
58a0e11
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
58a0e11
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
58a0e11
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
58a0e11
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
58a0e11
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
58a0e11
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
58a0e11
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
58a0e11
+ *     OTHER DEALINGS IN THE SOFTWARE.
58a0e11
+ */
58a0e11
+
58a0e11
+#include "sunxi-h3-h5.dtsi"
58a0e11
+
58a0e11
+/ {
58a0e11
+	cpus {
58a0e11
+		#address-cells = <1>;
58a0e11
+		#size-cells = <0>;
58a0e11
+
58a0e11
+		cpu@0 {
58a0e11
+			compatible = "arm,cortex-a7";
58a0e11
+			device_type = "cpu";
58a0e11
+			reg = <0>;
58a0e11
+		};
58a0e11
+
58a0e11
+		cpu@1 {
58a0e11
+			compatible = "arm,cortex-a7";
58a0e11
+			device_type = "cpu";
58a0e11
+			reg = <1>;
58a0e11
+		};
58a0e11
+
58a0e11
+		cpu@2 {
58a0e11
+			compatible = "arm,cortex-a7";
58a0e11
+			device_type = "cpu";
58a0e11
+			reg = <2>;
58a0e11
+		};
58a0e11
+
58a0e11
+		cpu@3 {
58a0e11
+			compatible = "arm,cortex-a7";
58a0e11
+			device_type = "cpu";
58a0e11
+			reg = <3>;
58a0e11
+		};
58a0e11
+	};
58a0e11
+
58a0e11
+	timer {
58a0e11
+		compatible = "arm,armv7-timer";
58a0e11
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58a0e11
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58a0e11
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58a0e11
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
58a0e11
+	};
58a0e11
+};
58a0e11
+
58a0e11
+&ccu {
58a0e11
+	compatible = "allwinner,sun8i-h3-ccu";
58a0e11
+};
58a0e11
+
58a0e11
+&mmc0 {
58a0e11
+	compatible = "allwinner,sun7i-a20-mmc";
58a0e11
+	clocks = <&ccu CLK_BUS_MMC0>,
58a0e11
+		 <&ccu CLK_MMC0>,
58a0e11
+		 <&ccu CLK_MMC0_OUTPUT>,
58a0e11
+		 <&ccu CLK_MMC0_SAMPLE>;
58a0e11
+	clock-names = "ahb",
58a0e11
+		      "mmc",
58a0e11
+		      "output",
58a0e11
+		      "sample";
58a0e11
+};
58a0e11
+
58a0e11
+&mmc1 {
58a0e11
+	compatible = "allwinner,sun7i-a20-mmc";
58a0e11
+	clocks = <&ccu CLK_BUS_MMC1>,
58a0e11
+		 <&ccu CLK_MMC1>,
58a0e11
+		 <&ccu CLK_MMC1_OUTPUT>,
58a0e11
+		 <&ccu CLK_MMC1_SAMPLE>;
58a0e11
+	clock-names = "ahb",
58a0e11
+		      "mmc",
58a0e11
+		      "output",
58a0e11
+		      "sample";
58a0e11
+};
58a0e11
+
58a0e11
+&mmc2 {
58a0e11
+	compatible = "allwinner,sun7i-a20-mmc";
58a0e11
+	clocks = <&ccu CLK_BUS_MMC2>,
58a0e11
+		 <&ccu CLK_MMC2>,
58a0e11
+		 <&ccu CLK_MMC2_OUTPUT>,
58a0e11
+		 <&ccu CLK_MMC2_SAMPLE>;
58a0e11
+	clock-names = "ahb",
58a0e11
+		      "mmc",
58a0e11
+		      "output",
58a0e11
+		      "sample";
58a0e11
+};
58a0e11
+
58a0e11
+&pio {
58a0e11
+	compatible = "allwinner,sun8i-h3-pinctrl";
58a0e11
+};
58a0e11
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
58a0e11
similarity index 90%
58a0e11
copy from arch/arm/boot/dts/sun8i-h3.dtsi
58a0e11
copy to arch/arm/boot/dts/sunxi-h3-h5.dtsi
58a0e11
index c13fbfb92592..2494ea063cd4 100644
58a0e11
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
58a0e11
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
58a0e11
@@ -46,43 +46,8 @@
58a0e11
 
58a0e11
 / {
58a0e11
 	interrupt-parent = <&gic;;
58a0e11
-
58a0e11
-	cpus {
58a0e11
-		#address-cells = <1>;
58a0e11
-		#size-cells = <0>;
58a0e11
-
58a0e11
-		cpu@0 {
58a0e11
-			compatible = "arm,cortex-a7";
58a0e11
-			device_type = "cpu";
58a0e11
-			reg = <0>;
58a0e11
-		};
58a0e11
-
58a0e11
-		cpu@1 {
58a0e11
-			compatible = "arm,cortex-a7";
58a0e11
-			device_type = "cpu";
58a0e11
-			reg = <1>;
58a0e11
-		};
58a0e11
-
58a0e11
-		cpu@2 {
58a0e11
-			compatible = "arm,cortex-a7";
58a0e11
-			device_type = "cpu";
58a0e11
-			reg = <2>;
58a0e11
-		};
58a0e11
-
58a0e11
-		cpu@3 {
58a0e11
-			compatible = "arm,cortex-a7";
58a0e11
-			device_type = "cpu";
58a0e11
-			reg = <3>;
58a0e11
-		};
58a0e11
-	};
58a0e11
-
58a0e11
-	timer {
58a0e11
-		compatible = "arm,armv7-timer";
58a0e11
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58a0e11
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58a0e11
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58a0e11
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
58a0e11
-	};
58a0e11
+	#address-cells = <1>;
58a0e11
+	#size-cells = <1>;
58a0e11
 
58a0e11
 	clocks {
58a0e11
 		#address-cells = <1>;
58a0e11
@@ -147,16 +112,8 @@
58a0e11
 		};
58a0e11
 
58a0e11
 		mmc0: mmc@01c0f000 {
58a0e11
-			compatible = "allwinner,sun7i-a20-mmc";
58a0e11
+			/* compatible and clocks are in per SoC .dtsi file */
58a0e11
 			reg = <0x01c0f000 0x1000>;
58a0e11
-			clocks = <&ccu CLK_BUS_MMC0>,
58a0e11
-				 <&ccu CLK_MMC0>,
58a0e11
-				 <&ccu CLK_MMC0_OUTPUT>,
58a0e11
-				 <&ccu CLK_MMC0_SAMPLE>;
58a0e11
-			clock-names = "ahb",
58a0e11
-				      "mmc",
58a0e11
-				      "output",
58a0e11
-				      "sample";
58a0e11
 			resets = <&ccu RST_BUS_MMC0>;
58a0e11
 			reset-names = "ahb";
58a0e11
 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
@@ -166,16 +123,8 @@
58a0e11
 		};
58a0e11
 
58a0e11
 		mmc1: mmc@01c10000 {
58a0e11
-			compatible = "allwinner,sun7i-a20-mmc";
58a0e11
+			/* compatible and clocks are in per SoC .dtsi file */
58a0e11
 			reg = <0x01c10000 0x1000>;
58a0e11
-			clocks = <&ccu CLK_BUS_MMC1>,
58a0e11
-				 <&ccu CLK_MMC1>,
58a0e11
-				 <&ccu CLK_MMC1_OUTPUT>,
58a0e11
-				 <&ccu CLK_MMC1_SAMPLE>;
58a0e11
-			clock-names = "ahb",
58a0e11
-				      "mmc",
58a0e11
-				      "output",
58a0e11
-				      "sample";
58a0e11
 			resets = <&ccu RST_BUS_MMC1>;
58a0e11
 			reset-names = "ahb";
58a0e11
 			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
@@ -185,16 +134,8 @@
58a0e11
 		};
58a0e11
 
58a0e11
 		mmc2: mmc@01c11000 {
58a0e11
-			compatible = "allwinner,sun7i-a20-mmc";
58a0e11
+			/* compatible and clocks are in per SoC .dtsi file */
58a0e11
 			reg = <0x01c11000 0x1000>;
58a0e11
-			clocks = <&ccu CLK_BUS_MMC2>,
58a0e11
-				 <&ccu CLK_MMC2>,
58a0e11
-				 <&ccu CLK_MMC2_OUTPUT>,
58a0e11
-				 <&ccu CLK_MMC2_SAMPLE>;
58a0e11
-			clock-names = "ahb",
58a0e11
-				      "mmc",
58a0e11
-				      "output",
58a0e11
-				      "sample";
58a0e11
 			resets = <&ccu RST_BUS_MMC2>;
58a0e11
 			reset-names = "ahb";
58a0e11
 			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
58a0e11
@@ -305,7 +246,7 @@
58a0e11
 		};
58a0e11
 
58a0e11
 		ccu: clock@01c20000 {
58a0e11
-			compatible = "allwinner,sun8i-h3-ccu";
58a0e11
+			/* compatible is in per SoC .dtsi file */
58a0e11
 			reg = <0x01c20000 0x400>;
58a0e11
 			clocks = <&osc24M>, <&osc32k>;
58a0e11
 			clock-names = "hosc", "losc";
58a0e11
@@ -314,7 +255,7 @@
58a0e11
 		};
58a0e11
 
58a0e11
 		pio: pinctrl@01c20800 {
58a0e11
-			compatible = "allwinner,sun8i-h3-pinctrl";
58a0e11
+			/* compatible is in per SoC .dtsi file */
58a0e11
 			reg = <0x01c20800 0x400>;
58a0e11
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
58a0e11
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;