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From patchwork Wed Mar 8 09:19:01 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v4,1/7] dt-bindings: Add binding for brcm,bcm2835-sdhost.
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From: Gerd Hoffmann <kraxel@redhat.com>
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X-Patchwork-Id: 9610673
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Message-Id: <1488964751-22763-2-git-send-email-kraxel@redhat.com>
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To: linux-rpi-kernel@lists.infradead.org
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Cc: mark.rutland@arm.com, stefan.wahren@i2se.com, ulf.hansson@linaro.org,
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f.fainelli@gmail.com, sbranden@broadcom.com, devicetree@vger.kernel.org,
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d85c975 |
rjui@broadcom.com, lee@kernel.org, will.deacon@arm.com,
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d85c975 |
linux@armlinux.org.uk,
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linux-kernel@vger.kernel.org, eric@anholt.net, robh+dt@kernel.org,
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bcm-kernel-feedback-list@broadcom.com, Gerd Hoffmann <kraxel@redhat.com>,
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catalin.marinas@arm.com, linux-mmc@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org
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Date: Wed, 8 Mar 2017 10:19:01 +0100
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From: Eric Anholt <eric@anholt.net>
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This is the other SD controller on the platform, which can be swapped
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to the role of SD card host using pin muxing.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Acked-by: Rob Herring <robh@kernel.org>
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---
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.../bindings/mmc/brcm,bcm2835-sdhost.txt | 23 ++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhost.txt
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diff --git a/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhost.txt b/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhost.txt
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new file mode 100644
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index 0000000..d876580
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhost.txt
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@@ -0,0 +1,23 @@
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+Broadcom BCM2835 SDHOST controller
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+
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+This file documents differences between the core properties described
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+by mmc.txt and the properties that represent the BCM2835 controller.
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+
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+Required properties:
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+- compatible: Should be "brcm,bcm2835-sdhost".
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+- clocks: The clock feeding the SDHOST controller.
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+
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+Optional properties:
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+- dmas: DMA channel for read and write.
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+ See Documentation/devicetree/bindings/dma/dma.txt for details
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+
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+Example:
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+
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+sdhost: mmc@7e202000 {
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+ compatible = "brcm,bcm2835-sdhost";
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+ reg = <0x7e202000 0x100>;
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+ interrupts = <2 24>;
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+ clocks = <&clocks BCM2835_CLOCK_VPU>;
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+ dmas = <&dma 13>;
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+ dma-names = "rx-tx";
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+};
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From patchwork Wed Mar 8 09:19:03 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v4,2/7] mmc: bcm2835: Add new driver for the sdhost controller.
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From: Gerd Hoffmann <kraxel@redhat.com>
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X-Patchwork-Id: 9610701
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Message-Id: <1488964751-22763-4-git-send-email-kraxel@redhat.com>
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To: linux-rpi-kernel@lists.infradead.org
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d85c975 |
Cc: mark.rutland@arm.com, stefan.wahren@i2se.com, ulf.hansson@linaro.org,
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d85c975 |
f.fainelli@gmail.com, sbranden@broadcom.com, devicetree@vger.kernel.org,
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d85c975 |
rjui@broadcom.com, lee@kernel.org, will.deacon@arm.com,
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d85c975 |
linux@armlinux.org.uk,
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d85c975 |
linux-kernel@vger.kernel.org, eric@anholt.net, robh+dt@kernel.org,
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bcm-kernel-feedback-list@broadcom.com, Gerd Hoffmann <kraxel@redhat.com>,
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catalin.marinas@arm.com, linux-mmc@vger.kernel.org,
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d85c975 |
linux-arm-kernel@lists.infradead.org
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Date: Wed, 8 Mar 2017 10:19:03 +0100
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From: Eric Anholt <eric@anholt.net>
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The 2835 has two SD controllers: The Arasan sdhci controller (supported
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by the iproc driver) and a custom sdhost controller. This patch adds a
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driver for the latter.
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The sdhci controller supports both sdcard and sdio. The sdhost
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controller supports the sdcard only, but has better performance. Also
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note that the rpi3 has sdio wifi, so driving the sdcard with the sdhost
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controller allows to use the sdhci controller for wifi support.
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The configuration is done by devicetree via pin muxing. Both SD
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controller are available on the same pins (2 pin groups = pin 22 to 27 +
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pin 48 to 53). So it's possible to use both SD controllers at the same
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time with different pin groups.
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d85c975 |
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The code was originally written by Phil Elwell in the downstream
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Rasbperry Pi tree. In preparation for the upstream merge it was
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cleaned up and the code base was moderized by Eric Anholt, Stefan
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Wahren and Gerd Hoffmann.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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---
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drivers/mmc/host/Kconfig | 14 +
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drivers/mmc/host/Makefile | 1 +
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drivers/mmc/host/bcm2835.c | 1465 ++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 1480 insertions(+)
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create mode 100644 drivers/mmc/host/bcm2835.c
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diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
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index f08691a..a638cd0 100644
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--- a/drivers/mmc/host/Kconfig
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+++ b/drivers/mmc/host/Kconfig
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@@ -799,6 +799,20 @@ config MMC_TOSHIBA_PCI
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depends on PCI
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help
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+config MMC_BCM2835
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+ tristate "Broadcom BCM2835 SDHOST MMC Controller support"
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+ depends on ARCH_BCM2835 || COMPILE_TEST
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+ depends on HAS_DMA
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+ help
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+ This selects the BCM2835 SDHOST MMC controller. If you have
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+ a BCM2835 platform with SD or MMC devices, say Y or M here.
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+
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+ Note that the BCM2835 has two SD controllers: The Arasan
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+ sdhci controller (supported by MMC_SDHCI_IPROC) and a custom
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+ sdhost controller (supported by this driver).
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+
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+ If unsure, say N.
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+
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config MMC_MTK
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tristate "MediaTek SD/MMC Card Interface support"
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depends on HAS_DMA
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diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
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index 6d548c4..bc2c2e2 100644
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--- a/drivers/mmc/host/Makefile
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+++ b/drivers/mmc/host/Makefile
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@@ -59,6 +59,7 @@ obj-$(CONFIG_MMC_MOXART) += moxart-mmc.o
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obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
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obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o
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obj-$(CONFIG_MMC_TOSHIBA_PCI) += toshsd.o
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+obj-$(CONFIG_MMC_BCM2835) += bcm2835.o
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obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
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obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
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diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c
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new file mode 100644
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index 0000000..7d1b0db7
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--- /dev/null
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+++ b/drivers/mmc/host/bcm2835.c
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@@ -0,0 +1,1465 @@
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+/*
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+ * bcm2835 sdhost driver.
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+ *
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+ * The 2835 has two SD controllers: The Arasan sdhci controller
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+ * (supported by the iproc driver) and a custom sdhost controller
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+ * (supported by this driver).
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+ *
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+ * The sdhci controller supports both sdcard and sdio. The sdhost
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+ * controller supports the sdcard only, but has better performance.
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+ * Also note that the rpi3 has sdio wifi, so driving the sdcard with
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+ * the sdhost controller allows to use the sdhci controller for wifi
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+ * support.
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+ *
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+ * The configuration is done by devicetree via pin muxing. Both
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+ * SD controller are available on the same pins (2 pin groups = pin 22
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+ * to 27 + pin 48 to 53). So it's possible to use both SD controllers
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+ * at the same time with different pin groups.
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+ *
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+ * Author: Phil Elwell <phil@raspberrypi.org>
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+ * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
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+ *
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+ * Based on
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+ * mmc-bcm2835.c by Gellert Weisz
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+ * which is, in turn, based on
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+ * sdhci-bcm2708.c by Broadcom
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+ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
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+ * sdhci.c and sdhci-pci.c by Pierre Ossman
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/device.h>
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+#include <linux/dmaengine.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/err.h>
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+#include <linux/highmem.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/iopoll.h>
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+#include <linux/module.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+#include <linux/platform_device.h>
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+#include <linux/scatterlist.h>
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+#include <linux/time.h>
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+#include <linux/workqueue.h>
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+
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+#include <linux/mmc/host.h>
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+#include <linux/mmc/mmc.h>
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+#include <linux/mmc/sd.h>
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+
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+#define SDCMD 0x00 /* Command to SD card - 16 R/W */
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+#define SDARG 0x04 /* Argument to SD card - 32 R/W */
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+#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
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+#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
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+#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
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+#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
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+#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
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+#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
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+#define SDHSTS 0x20 /* SD host status - 11 R/W */
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+#define SDVDD 0x30 /* SD card power control - 1 R/W */
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+#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
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+#define SDHCFG 0x38 /* Host configuration - 2 R/W */
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+#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
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+#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
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+#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
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+
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+#define SDCMD_NEW_FLAG 0x8000
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+#define SDCMD_FAIL_FLAG 0x4000
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+#define SDCMD_BUSYWAIT 0x800
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+#define SDCMD_NO_RESPONSE 0x400
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+#define SDCMD_LONG_RESPONSE 0x200
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+#define SDCMD_WRITE_CMD 0x80
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+#define SDCMD_READ_CMD 0x40
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+#define SDCMD_CMD_MASK 0x3f
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+
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+#define SDCDIV_MAX_CDIV 0x7ff
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+
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+#define SDHSTS_BUSY_IRPT 0x400
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+#define SDHSTS_BLOCK_IRPT 0x200
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+#define SDHSTS_SDIO_IRPT 0x100
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+#define SDHSTS_REW_TIME_OUT 0x80
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+#define SDHSTS_CMD_TIME_OUT 0x40
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+#define SDHSTS_CRC16_ERROR 0x20
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+#define SDHSTS_CRC7_ERROR 0x10
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+#define SDHSTS_FIFO_ERROR 0x08
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+/* Reserved */
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d85c975 |
+/* Reserved */
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d85c975 |
+#define SDHSTS_DATA_FLAG 0x01
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
|
|
|
d85c975 |
+ SDHSTS_CRC16_ERROR | \
|
|
|
d85c975 |
+ SDHSTS_REW_TIME_OUT | \
|
|
|
d85c975 |
+ SDHSTS_FIFO_ERROR)
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
|
|
|
d85c975 |
+ SDHSTS_TRANSFER_ERROR_MASK)
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define SDHCFG_BUSY_IRPT_EN BIT(10)
|
|
|
d85c975 |
+#define SDHCFG_BLOCK_IRPT_EN BIT(8)
|
|
|
d85c975 |
+#define SDHCFG_SDIO_IRPT_EN BIT(5)
|
|
|
d85c975 |
+#define SDHCFG_DATA_IRPT_EN BIT(4)
|
|
|
d85c975 |
+#define SDHCFG_SLOW_CARD BIT(3)
|
|
|
d85c975 |
+#define SDHCFG_WIDE_EXT_BUS BIT(2)
|
|
|
d85c975 |
+#define SDHCFG_WIDE_INT_BUS BIT(1)
|
|
|
d85c975 |
+#define SDHCFG_REL_CMD_LINE BIT(0)
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define SDVDD_POWER_OFF 0
|
|
|
d85c975 |
+#define SDVDD_POWER_ON 1
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define SDEDM_FORCE_DATA_MODE BIT(19)
|
|
|
d85c975 |
+#define SDEDM_CLOCK_PULSE BIT(20)
|
|
|
d85c975 |
+#define SDEDM_BYPASS BIT(21)
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define SDEDM_WRITE_THRESHOLD_SHIFT 9
|
|
|
d85c975 |
+#define SDEDM_READ_THRESHOLD_SHIFT 14
|
|
|
d85c975 |
+#define SDEDM_THRESHOLD_MASK 0x1f
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define SDEDM_FSM_MASK 0xf
|
|
|
d85c975 |
+#define SDEDM_FSM_IDENTMODE 0x0
|
|
|
d85c975 |
+#define SDEDM_FSM_DATAMODE 0x1
|
|
|
d85c975 |
+#define SDEDM_FSM_READDATA 0x2
|
|
|
d85c975 |
+#define SDEDM_FSM_WRITEDATA 0x3
|
|
|
d85c975 |
+#define SDEDM_FSM_READWAIT 0x4
|
|
|
d85c975 |
+#define SDEDM_FSM_READCRC 0x5
|
|
|
d85c975 |
+#define SDEDM_FSM_WRITECRC 0x6
|
|
|
d85c975 |
+#define SDEDM_FSM_WRITEWAIT1 0x7
|
|
|
d85c975 |
+#define SDEDM_FSM_POWERDOWN 0x8
|
|
|
d85c975 |
+#define SDEDM_FSM_POWERUP 0x9
|
|
|
d85c975 |
+#define SDEDM_FSM_WRITESTART1 0xa
|
|
|
d85c975 |
+#define SDEDM_FSM_WRITESTART2 0xb
|
|
|
d85c975 |
+#define SDEDM_FSM_GENPULSES 0xc
|
|
|
d85c975 |
+#define SDEDM_FSM_WRITEWAIT2 0xd
|
|
|
d85c975 |
+#define SDEDM_FSM_STARTPOWDOWN 0xf
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define SDDATA_FIFO_WORDS 16
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define FIFO_READ_THRESHOLD 4
|
|
|
d85c975 |
+#define FIFO_WRITE_THRESHOLD 4
|
|
|
d85c975 |
+#define SDDATA_FIFO_PIO_BURST 8
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+#define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+struct bcm2835_host {
|
|
|
d85c975 |
+ spinlock_t lock;
|
|
|
d85c975 |
+ struct mutex mutex;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ void __iomem *ioaddr;
|
|
|
d85c975 |
+ u32 phys_addr;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ struct mmc_host *mmc;
|
|
|
d85c975 |
+ struct platform_device *pdev;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ int clock; /* Current clock speed */
|
|
|
d85c975 |
+ unsigned int max_clk; /* Max possible freq */
|
|
|
d85c975 |
+ struct work_struct dma_work;
|
|
|
d85c975 |
+ struct delayed_work timeout_work; /* Timer for timeouts */
|
|
|
d85c975 |
+ struct sg_mapping_iter sg_miter; /* SG state for PIO */
|
|
|
d85c975 |
+ unsigned int blocks; /* remaining PIO blocks */
|
|
|
d85c975 |
+ int irq; /* Device IRQ */
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ u32 ns_per_fifo_word;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* cached registers */
|
|
|
d85c975 |
+ u32 hcfg;
|
|
|
d85c975 |
+ u32 cdiv;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ struct mmc_request *mrq; /* Current request */
|
|
|
d85c975 |
+ struct mmc_command *cmd; /* Current command */
|
|
|
d85c975 |
+ struct mmc_data *data; /* Current data request */
|
|
|
d85c975 |
+ bool data_complete:1;/* Data finished before cmd */
|
|
|
d85c975 |
+ bool use_busy:1; /* Wait for busy interrupt */
|
|
|
d85c975 |
+ bool use_sbc:1; /* Send CMD23 */
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* for threaded irq handler */
|
|
|
d85c975 |
+ bool irq_block;
|
|
|
d85c975 |
+ bool irq_busy;
|
|
|
d85c975 |
+ bool irq_data;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* DMA part */
|
|
|
d85c975 |
+ struct dma_chan *dma_chan_rxtx;
|
|
|
d85c975 |
+ struct dma_chan *dma_chan;
|
|
|
d85c975 |
+ struct dma_slave_config dma_cfg_rx;
|
|
|
d85c975 |
+ struct dma_slave_config dma_cfg_tx;
|
|
|
d85c975 |
+ struct dma_async_tx_descriptor *dma_desc;
|
|
|
d85c975 |
+ u32 dma_dir;
|
|
|
d85c975 |
+ u32 drain_words;
|
|
|
d85c975 |
+ struct page *drain_page;
|
|
|
d85c975 |
+ u32 drain_offset;
|
|
|
d85c975 |
+ bool use_dma;
|
|
|
d85c975 |
+};
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd,
|
|
|
d85c975 |
+ const char *label)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!cmd)
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
|
|
|
d85c975 |
+ (cmd == host->cmd) ? '>' : ' ',
|
|
|
d85c975 |
+ label, cmd->opcode, cmd->arg, cmd->flags,
|
|
|
d85c975 |
+ cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
|
|
|
d85c975 |
+ cmd->error);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_dumpregs(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct mmc_request *mrq = host->mrq;
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (mrq) {
|
|
|
d85c975 |
+ bcm2835_dumpcmd(host, mrq->sbc, "sbc");
|
|
|
d85c975 |
+ bcm2835_dumpcmd(host, mrq->cmd, "cmd");
|
|
|
d85c975 |
+ if (mrq->data) {
|
|
|
d85c975 |
+ dev_dbg(dev, "data blocks %x blksz %x - err %d\n",
|
|
|
d85c975 |
+ mrq->data->blocks,
|
|
|
d85c975 |
+ mrq->data->blksz,
|
|
|
d85c975 |
+ mrq->data->error);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ bcm2835_dumpcmd(host, mrq->stop, "stop");
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
|
|
|
d85c975 |
+ dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
|
|
|
d85c975 |
+ dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
|
|
|
d85c975 |
+ dev_dbg(dev, "===========================================\n");
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_reset_internal(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ u32 temp;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
|
|
|
d85c975 |
+ writel(0, host->ioaddr + SDCMD);
|
|
|
d85c975 |
+ writel(0, host->ioaddr + SDARG);
|
|
|
d85c975 |
+ writel(0xf00000, host->ioaddr + SDTOUT);
|
|
|
d85c975 |
+ writel(0, host->ioaddr + SDCDIV);
|
|
|
d85c975 |
+ writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */
|
|
|
d85c975 |
+ writel(0, host->ioaddr + SDHCFG);
|
|
|
d85c975 |
+ writel(0, host->ioaddr + SDHBCT);
|
|
|
d85c975 |
+ writel(0, host->ioaddr + SDHBLC);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Limit fifo usage due to silicon bug */
|
|
|
d85c975 |
+ temp = readl(host->ioaddr + SDEDM);
|
|
|
d85c975 |
+ temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
|
|
|
d85c975 |
+ (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
|
|
|
d85c975 |
+ temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
|
|
|
d85c975 |
+ (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
|
|
|
d85c975 |
+ writel(temp, host->ioaddr + SDEDM);
|
|
|
d85c975 |
+ msleep(20);
|
|
|
d85c975 |
+ writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
|
|
|
d85c975 |
+ msleep(20);
|
|
|
d85c975 |
+ host->clock = 0;
|
|
|
d85c975 |
+ writel(host->hcfg, host->ioaddr + SDHCFG);
|
|
|
d85c975 |
+ writel(host->cdiv, host->ioaddr + SDCDIV);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_reset(struct mmc_host *mmc)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct bcm2835_host *host = mmc_priv(mmc);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->dma_chan)
|
|
|
d85c975 |
+ dmaengine_terminate_sync(host->dma_chan);
|
|
|
d85c975 |
+ bcm2835_reset_internal(host);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_finish_command(struct bcm2835_host *host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ int timediff;
|
|
|
d85c975 |
+ u32 alternate_idle;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?
|
|
|
d85c975 |
+ SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ timediff = 0;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ while (1) {
|
|
|
d85c975 |
+ u32 edm, fsm;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ edm = readl(host->ioaddr + SDEDM);
|
|
|
d85c975 |
+ fsm = edm & SDEDM_FSM_MASK;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if ((fsm == SDEDM_FSM_IDENTMODE) ||
|
|
|
d85c975 |
+ (fsm == SDEDM_FSM_DATAMODE))
|
|
|
d85c975 |
+ break;
|
|
|
d85c975 |
+ if (fsm == alternate_idle) {
|
|
|
d85c975 |
+ writel(edm | SDEDM_FORCE_DATA_MODE,
|
|
|
d85c975 |
+ host->ioaddr + SDEDM);
|
|
|
d85c975 |
+ break;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ timediff++;
|
|
|
d85c975 |
+ if (timediff == 100000) {
|
|
|
d85c975 |
+ dev_err(&host->pdev->dev,
|
|
|
d85c975 |
+ "wait_transfer_complete - still waiting after %d retries\n",
|
|
|
d85c975 |
+ timediff);
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ host->mrq->data->error = -ETIMEDOUT;
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ cpu_relax();
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_dma_complete(void *param)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct bcm2835_host *host = param;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ schedule_work(&host->dma_work);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ unsigned long flags;
|
|
|
d85c975 |
+ size_t blksize;
|
|
|
d85c975 |
+ unsigned long wait_max;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ blksize = host->data->blksz;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ wait_max = jiffies + msecs_to_jiffies(500);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ local_irq_save(flags);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ while (blksize) {
|
|
|
d85c975 |
+ int copy_words;
|
|
|
d85c975 |
+ u32 hsts = 0;
|
|
|
d85c975 |
+ size_t len;
|
|
|
d85c975 |
+ u32 *buf;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!sg_miter_next(&host->sg_miter)) {
|
|
|
d85c975 |
+ host->data->error = -EINVAL;
|
|
|
d85c975 |
+ break;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ len = min(host->sg_miter.length, blksize);
|
|
|
d85c975 |
+ if (len % 4) {
|
|
|
d85c975 |
+ host->data->error = -EINVAL;
|
|
|
d85c975 |
+ break;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ blksize -= len;
|
|
|
d85c975 |
+ host->sg_miter.consumed = len;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ buf = (u32 *)host->sg_miter.addr;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ copy_words = len / 4;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ while (copy_words) {
|
|
|
d85c975 |
+ int burst_words, words;
|
|
|
d85c975 |
+ u32 edm;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
|
|
|
d85c975 |
+ edm = readl(host->ioaddr + SDEDM);
|
|
|
d85c975 |
+ if (is_read)
|
|
|
d85c975 |
+ words = ((edm >> 4) & 0x1f);
|
|
|
d85c975 |
+ else
|
|
|
d85c975 |
+ words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (words < burst_words) {
|
|
|
d85c975 |
+ int fsm_state = (edm & SDEDM_FSM_MASK);
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if ((is_read &&
|
|
|
d85c975 |
+ (fsm_state != SDEDM_FSM_READDATA &&
|
|
|
d85c975 |
+ fsm_state != SDEDM_FSM_READWAIT &&
|
|
|
d85c975 |
+ fsm_state != SDEDM_FSM_READCRC)) ||
|
|
|
d85c975 |
+ (!is_read &&
|
|
|
d85c975 |
+ (fsm_state != SDEDM_FSM_WRITEDATA &&
|
|
|
d85c975 |
+ fsm_state != SDEDM_FSM_WRITESTART1 &&
|
|
|
d85c975 |
+ fsm_state != SDEDM_FSM_WRITESTART2))) {
|
|
|
d85c975 |
+ hsts = readl(host->ioaddr + SDHSTS);
|
|
|
d85c975 |
+ dev_err(dev, "fsm %x, hsts %08x\n",
|
|
|
d85c975 |
+ fsm_state, hsts);
|
|
|
d85c975 |
+ if (hsts & SDHSTS_ERROR_MASK)
|
|
|
d85c975 |
+ break;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (time_after(jiffies, wait_max)) {
|
|
|
d85c975 |
+ dev_err(dev, "PIO %s timeout - EDM %08x\n",
|
|
|
d85c975 |
+ is_read ? "read" : "write",
|
|
|
d85c975 |
+ edm);
|
|
|
d85c975 |
+ hsts = SDHSTS_REW_TIME_OUT;
|
|
|
d85c975 |
+ break;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ ndelay((burst_words - words) *
|
|
|
d85c975 |
+ host->ns_per_fifo_word);
|
|
|
d85c975 |
+ continue;
|
|
|
d85c975 |
+ } else if (words > copy_words) {
|
|
|
d85c975 |
+ words = copy_words;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ copy_words -= words;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ while (words) {
|
|
|
d85c975 |
+ if (is_read)
|
|
|
d85c975 |
+ *(buf++) = readl(host->ioaddr + SDDATA);
|
|
|
d85c975 |
+ else
|
|
|
d85c975 |
+ writel(*(buf++), host->ioaddr + SDDATA);
|
|
|
d85c975 |
+ words--;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (hsts & SDHSTS_ERROR_MASK)
|
|
|
d85c975 |
+ break;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ sg_miter_stop(&host->sg_miter);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ local_irq_restore(flags);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_transfer_pio(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+ u32 sdhsts;
|
|
|
d85c975 |
+ bool is_read;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ is_read = (host->data->flags & MMC_DATA_READ) != 0;
|
|
|
d85c975 |
+ bcm2835_transfer_block_pio(host, is_read);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ sdhsts = readl(host->ioaddr + SDHSTS);
|
|
|
d85c975 |
+ if (sdhsts & (SDHSTS_CRC16_ERROR |
|
|
|
d85c975 |
+ SDHSTS_CRC7_ERROR |
|
|
|
d85c975 |
+ SDHSTS_FIFO_ERROR)) {
|
|
|
d85c975 |
+ dev_err(dev, "%s transfer error - HSTS %08x\n",
|
|
|
d85c975 |
+ is_read ? "read" : "write", sdhsts);
|
|
|
d85c975 |
+ host->data->error = -EILSEQ;
|
|
|
d85c975 |
+ } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
|
|
|
d85c975 |
+ SDHSTS_REW_TIME_OUT))) {
|
|
|
d85c975 |
+ dev_err(dev, "%s timeout error - HSTS %08x\n",
|
|
|
d85c975 |
+ is_read ? "read" : "write", sdhsts);
|
|
|
d85c975 |
+ host->data->error = -ETIMEDOUT;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static
|
|
|
d85c975 |
+void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ int len, dir_data, dir_slave;
|
|
|
d85c975 |
+ struct dma_async_tx_descriptor *desc = NULL;
|
|
|
d85c975 |
+ struct dma_chan *dma_chan;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ dma_chan = host->dma_chan_rxtx;
|
|
|
d85c975 |
+ if (data->flags & MMC_DATA_READ) {
|
|
|
d85c975 |
+ dir_data = DMA_FROM_DEVICE;
|
|
|
d85c975 |
+ dir_slave = DMA_DEV_TO_MEM;
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ dir_data = DMA_TO_DEVICE;
|
|
|
d85c975 |
+ dir_slave = DMA_MEM_TO_DEV;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* The block doesn't manage the FIFO DREQs properly for
|
|
|
d85c975 |
+ * multi-block transfers, so don't attempt to DMA the final
|
|
|
d85c975 |
+ * few words. Unfortunately this requires the final sg entry
|
|
|
d85c975 |
+ * to be trimmed. N.B. This code demands that the overspill
|
|
|
d85c975 |
+ * is contained in a single sg entry.
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->drain_words = 0;
|
|
|
d85c975 |
+ if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {
|
|
|
d85c975 |
+ struct scatterlist *sg;
|
|
|
d85c975 |
+ u32 len;
|
|
|
d85c975 |
+ int i;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,
|
|
|
d85c975 |
+ (u32)data->blocks * data->blksz);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ for_each_sg(data->sg, sg, data->sg_len, i) {
|
|
|
d85c975 |
+ if (sg_is_last(sg)) {
|
|
|
d85c975 |
+ WARN_ON(sg->length < len);
|
|
|
d85c975 |
+ sg->length -= len;
|
|
|
d85c975 |
+ host->drain_page = sg_page(sg);
|
|
|
d85c975 |
+ host->drain_offset = sg->offset + sg->length;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ host->drain_words = len / 4;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* The parameters have already been validated, so this will not fail */
|
|
|
d85c975 |
+ (void)dmaengine_slave_config(dma_chan,
|
|
|
d85c975 |
+ (dir_data == DMA_FROM_DEVICE) ?
|
|
|
d85c975 |
+ &host->dma_cfg_rx :
|
|
|
d85c975 |
+ &host->dma_cfg_tx);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
|
|
|
d85c975 |
+ dir_data);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (len > 0) {
|
|
|
d85c975 |
+ desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
|
|
|
d85c975 |
+ len, dir_slave,
|
|
|
d85c975 |
+ DMA_PREP_INTERRUPT |
|
|
|
d85c975 |
+ DMA_CTRL_ACK);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (desc) {
|
|
|
d85c975 |
+ desc->callback = bcm2835_dma_complete;
|
|
|
d85c975 |
+ desc->callback_param = host;
|
|
|
d85c975 |
+ host->dma_desc = desc;
|
|
|
d85c975 |
+ host->dma_chan = dma_chan;
|
|
|
d85c975 |
+ host->dma_dir = dir_data;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_start_dma(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ dmaengine_submit(host->dma_desc);
|
|
|
d85c975 |
+ dma_async_issue_pending(host->dma_chan);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
|
|
|
d85c975 |
+ SDHCFG_BUSY_IRPT_EN;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->dma_desc) {
|
|
|
d85c975 |
+ host->hcfg = (host->hcfg & ~all_irqs) |
|
|
|
d85c975 |
+ SDHCFG_BUSY_IRPT_EN;
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ host->hcfg = (host->hcfg & ~all_irqs) |
|
|
|
d85c975 |
+ SDHCFG_DATA_IRPT_EN |
|
|
|
d85c975 |
+ SDHCFG_BUSY_IRPT_EN;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ writel(host->hcfg, host->ioaddr + SDHCFG);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static
|
|
|
d85c975 |
+void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct mmc_data *data = cmd->data;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ WARN_ON(host->data);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->data = data;
|
|
|
d85c975 |
+ if (!data)
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->data_complete = false;
|
|
|
d85c975 |
+ host->data->bytes_xfered = 0;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!host->dma_desc) {
|
|
|
d85c975 |
+ /* Use PIO */
|
|
|
d85c975 |
+ int flags = SG_MITER_ATOMIC;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (data->flags & MMC_DATA_READ)
|
|
|
d85c975 |
+ flags |= SG_MITER_TO_SG;
|
|
|
d85c975 |
+ else
|
|
|
d85c975 |
+ flags |= SG_MITER_FROM_SG;
|
|
|
d85c975 |
+ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
|
|
|
d85c975 |
+ host->blocks = data->blocks;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ bcm2835_set_transfer_irqs(host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ writel(data->blksz, host->ioaddr + SDHBCT);
|
|
|
d85c975 |
+ writel(data->blocks, host->ioaddr + SDHBLC);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+ u32 value;
|
|
|
d85c975 |
+ int ret;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
|
|
|
d85c975 |
+ !(value & SDCMD_NEW_FLAG), 1, 10);
|
|
|
d85c975 |
+ if (ret == -ETIMEDOUT)
|
|
|
d85c975 |
+ /* if it takes a while make poll interval bigger */
|
|
|
d85c975 |
+ ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
|
|
|
d85c975 |
+ !(value & SDCMD_NEW_FLAG),
|
|
|
d85c975 |
+ 10, max_ms * 1000);
|
|
|
d85c975 |
+ if (ret == -ETIMEDOUT)
|
|
|
d85c975 |
+ dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ return value;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_finish_request(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct dma_chan *terminate_chan = NULL;
|
|
|
d85c975 |
+ struct mmc_request *mrq;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ cancel_delayed_work(&host->timeout_work);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mrq = host->mrq;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->mrq = NULL;
|
|
|
d85c975 |
+ host->cmd = NULL;
|
|
|
d85c975 |
+ host->data = NULL;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->dma_desc = NULL;
|
|
|
d85c975 |
+ terminate_chan = host->dma_chan;
|
|
|
d85c975 |
+ host->dma_chan = NULL;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (terminate_chan) {
|
|
|
d85c975 |
+ int err = dmaengine_terminate_all(terminate_chan);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (err)
|
|
|
d85c975 |
+ dev_err(&host->pdev->dev,
|
|
|
d85c975 |
+ "failed to terminate DMA (%d)\n", err);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mmc_request_done(host->mmc, mrq);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static
|
|
|
d85c975 |
+bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+ u32 sdcmd, sdhsts;
|
|
|
d85c975 |
+ unsigned long timeout;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ WARN_ON(host->cmd);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ sdcmd = bcm2835_read_wait_sdcmd(host, 100);
|
|
|
d85c975 |
+ if (sdcmd & SDCMD_NEW_FLAG) {
|
|
|
d85c975 |
+ dev_err(dev, "previous command never completed.\n");
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ cmd->error = -EILSEQ;
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ return false;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!cmd->data && cmd->busy_timeout > 9000)
|
|
|
d85c975 |
+ timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
|
|
|
d85c975 |
+ else
|
|
|
d85c975 |
+ timeout = 10 * HZ;
|
|
|
d85c975 |
+ schedule_delayed_work(&host->timeout_work, timeout);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->cmd = cmd;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Clear any error flags */
|
|
|
d85c975 |
+ sdhsts = readl(host->ioaddr + SDHSTS);
|
|
|
d85c975 |
+ if (sdhsts & SDHSTS_ERROR_MASK)
|
|
|
d85c975 |
+ writel(sdhsts, host->ioaddr + SDHSTS);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
|
|
|
d85c975 |
+ dev_err(dev, "unsupported response type!\n");
|
|
|
d85c975 |
+ cmd->error = -EINVAL;
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ return false;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ bcm2835_prepare_data(host, cmd);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ writel(cmd->arg, host->ioaddr + SDARG);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ sdcmd = cmd->opcode & SDCMD_CMD_MASK;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->use_busy = false;
|
|
|
d85c975 |
+ if (!(cmd->flags & MMC_RSP_PRESENT)) {
|
|
|
d85c975 |
+ sdcmd |= SDCMD_NO_RESPONSE;
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ if (cmd->flags & MMC_RSP_136)
|
|
|
d85c975 |
+ sdcmd |= SDCMD_LONG_RESPONSE;
|
|
|
d85c975 |
+ if (cmd->flags & MMC_RSP_BUSY) {
|
|
|
d85c975 |
+ sdcmd |= SDCMD_BUSYWAIT;
|
|
|
d85c975 |
+ host->use_busy = true;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (cmd->data) {
|
|
|
d85c975 |
+ if (cmd->data->flags & MMC_DATA_WRITE)
|
|
|
d85c975 |
+ sdcmd |= SDCMD_WRITE_CMD;
|
|
|
d85c975 |
+ if (cmd->data->flags & MMC_DATA_READ)
|
|
|
d85c975 |
+ sdcmd |= SDCMD_READ_CMD;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ return true;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_transfer_complete(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct mmc_data *data;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ WARN_ON(!host->data_complete);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ data = host->data;
|
|
|
d85c975 |
+ host->data = NULL;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Need to send CMD12 if -
|
|
|
d85c975 |
+ * a) open-ended multiblock transfer (no CMD23)
|
|
|
d85c975 |
+ * b) error in multiblock transfer
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+ if (host->mrq->stop && (data->error || !host->use_sbc)) {
|
|
|
d85c975 |
+ if (bcm2835_send_command(host, host->mrq->stop)) {
|
|
|
d85c975 |
+ /* No busy, so poll for completion */
|
|
|
d85c975 |
+ if (!host->use_busy)
|
|
|
d85c975 |
+ bcm2835_finish_command(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ bcm2835_wait_transfer_complete(host);
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_finish_data(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+ struct mmc_data *data;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ data = host->data;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
|
|
|
d85c975 |
+ writel(host->hcfg, host->ioaddr + SDHCFG);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->data_complete = true;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->cmd) {
|
|
|
d85c975 |
+ /* Data managed to finish before the
|
|
|
d85c975 |
+ * command completed. Make sure we do
|
|
|
d85c975 |
+ * things in the proper order.
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+ dev_dbg(dev, "Finished early - HSTS %08x\n",
|
|
|
d85c975 |
+ readl(host->ioaddr + SDHSTS));
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ bcm2835_transfer_complete(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_finish_command(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+ struct mmc_command *cmd = host->cmd;
|
|
|
d85c975 |
+ u32 sdcmd;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ sdcmd = bcm2835_read_wait_sdcmd(host, 100);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Check for errors */
|
|
|
d85c975 |
+ if (sdcmd & SDCMD_NEW_FLAG) {
|
|
|
d85c975 |
+ dev_err(dev, "command never completed.\n");
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ host->cmd->error = -EIO;
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ } else if (sdcmd & SDCMD_FAIL_FLAG) {
|
|
|
d85c975 |
+ u32 sdhsts = readl(host->ioaddr + SDHSTS);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Clear the errors */
|
|
|
d85c975 |
+ writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
|
|
|
d85c975 |
+ (host->cmd->opcode != MMC_SEND_OP_COND)) {
|
|
|
d85c975 |
+ if (sdhsts & SDHSTS_CMD_TIME_OUT) {
|
|
|
d85c975 |
+ host->cmd->error = -ETIMEDOUT;
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ dev_err(dev, "unexpected command %d error\n",
|
|
|
d85c975 |
+ host->cmd->opcode);
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ host->cmd->error = -EILSEQ;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (cmd->flags & MMC_RSP_PRESENT) {
|
|
|
d85c975 |
+ if (cmd->flags & MMC_RSP_136) {
|
|
|
d85c975 |
+ int i;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ for (i = 0; i < 4; i++) {
|
|
|
d85c975 |
+ cmd->resp[3 - i] =
|
|
|
d85c975 |
+ readl(host->ioaddr + SDRSP0 + i * 4);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ cmd->resp[0] = readl(host->ioaddr + SDRSP0);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (cmd == host->mrq->sbc) {
|
|
|
d85c975 |
+ /* Finished CMD23, now send actual command. */
|
|
|
d85c975 |
+ host->cmd = NULL;
|
|
|
d85c975 |
+ if (bcm2835_send_command(host, host->mrq->cmd)) {
|
|
|
d85c975 |
+ if (host->data && host->dma_desc)
|
|
|
d85c975 |
+ /* DMA transfer starts now, PIO starts
|
|
|
d85c975 |
+ * after irq
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+ bcm2835_start_dma(host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!host->use_busy)
|
|
|
d85c975 |
+ bcm2835_finish_command(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ } else if (cmd == host->mrq->stop) {
|
|
|
d85c975 |
+ /* Finished CMD12 */
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ /* Processed actual command. */
|
|
|
d85c975 |
+ host->cmd = NULL;
|
|
|
d85c975 |
+ if (!host->data)
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ else if (host->data_complete)
|
|
|
d85c975 |
+ bcm2835_transfer_complete(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_timeout(struct work_struct *work)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct delayed_work *d = to_delayed_work(work);
|
|
|
d85c975 |
+ struct bcm2835_host *host =
|
|
|
d85c975 |
+ container_of(d, struct bcm2835_host, timeout_work);
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_lock(&host->mutex);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->mrq) {
|
|
|
d85c975 |
+ dev_err(dev, "timeout waiting for hardware interrupt.\n");
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->data) {
|
|
|
d85c975 |
+ host->data->error = -ETIMEDOUT;
|
|
|
d85c975 |
+ bcm2835_finish_data(host);
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ if (host->cmd)
|
|
|
d85c975 |
+ host->cmd->error = -ETIMEDOUT;
|
|
|
d85c975 |
+ else
|
|
|
d85c975 |
+ host->mrq->cmd->error = -ETIMEDOUT;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_unlock(&host->mutex);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!(intmask & SDHSTS_ERROR_MASK))
|
|
|
d85c975 |
+ return false;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!host->cmd)
|
|
|
d85c975 |
+ return true;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask);
|
|
|
d85c975 |
+ if (intmask & SDHSTS_CRC7_ERROR) {
|
|
|
d85c975 |
+ host->cmd->error = -EILSEQ;
|
|
|
d85c975 |
+ } else if (intmask & (SDHSTS_CRC16_ERROR |
|
|
|
d85c975 |
+ SDHSTS_FIFO_ERROR)) {
|
|
|
d85c975 |
+ if (host->mrq->data)
|
|
|
d85c975 |
+ host->mrq->data->error = -EILSEQ;
|
|
|
d85c975 |
+ else
|
|
|
d85c975 |
+ host->cmd->error = -EILSEQ;
|
|
|
d85c975 |
+ } else if (intmask & SDHSTS_REW_TIME_OUT) {
|
|
|
d85c975 |
+ if (host->mrq->data)
|
|
|
d85c975 |
+ host->mrq->data->error = -ETIMEDOUT;
|
|
|
d85c975 |
+ else
|
|
|
d85c975 |
+ host->cmd->error = -ETIMEDOUT;
|
|
|
d85c975 |
+ } else if (intmask & SDHSTS_CMD_TIME_OUT) {
|
|
|
d85c975 |
+ host->cmd->error = -ETIMEDOUT;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ return true;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ if (!host->data)
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
|
|
|
d85c975 |
+ host->data->error = -EILSEQ;
|
|
|
d85c975 |
+ if (intmask & SDHSTS_REW_TIME_OUT)
|
|
|
d85c975 |
+ host->data->error = -ETIMEDOUT;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_busy_irq(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ if (WARN_ON(!host->cmd)) {
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (WARN_ON(!host->use_busy)) {
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ host->use_busy = false;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ bcm2835_finish_command(host);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ /* There are no dedicated data/space available interrupt
|
|
|
d85c975 |
+ * status bits, so it is necessary to use the single shared
|
|
|
d85c975 |
+ * data/space available FIFO status bits. It is therefore not
|
|
|
d85c975 |
+ * an error to get here when there is no data transfer in
|
|
|
d85c975 |
+ * progress.
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+ if (!host->data)
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ bcm2835_check_data_error(host, intmask);
|
|
|
d85c975 |
+ if (host->data->error)
|
|
|
d85c975 |
+ goto finished;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->data->flags & MMC_DATA_WRITE) {
|
|
|
d85c975 |
+ /* Use the block interrupt for writes after the first block */
|
|
|
d85c975 |
+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
|
|
|
d85c975 |
+ host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
|
|
|
d85c975 |
+ writel(host->hcfg, host->ioaddr + SDHCFG);
|
|
|
d85c975 |
+ bcm2835_transfer_pio(host);
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ bcm2835_transfer_pio(host);
|
|
|
d85c975 |
+ host->blocks--;
|
|
|
d85c975 |
+ if ((host->blocks == 0) || host->data->error)
|
|
|
d85c975 |
+ goto finished;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+finished:
|
|
|
d85c975 |
+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
|
|
|
d85c975 |
+ writel(host->hcfg, host->ioaddr + SDHCFG);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ if (!host->data)
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ if ((host->blocks == 0) || host->data->error)
|
|
|
d85c975 |
+ bcm2835_finish_data(host);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_block_irq(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ if (WARN_ON(!host->data)) {
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!host->dma_desc) {
|
|
|
d85c975 |
+ WARN_ON(!host->blocks);
|
|
|
d85c975 |
+ if (host->data->error || (--host->blocks == 0))
|
|
|
d85c975 |
+ bcm2835_finish_data(host);
|
|
|
d85c975 |
+ else
|
|
|
d85c975 |
+ bcm2835_transfer_pio(host);
|
|
|
d85c975 |
+ } else if (host->data->flags & MMC_DATA_WRITE) {
|
|
|
d85c975 |
+ bcm2835_finish_data(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static irqreturn_t bcm2835_irq(int irq, void *dev_id)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ irqreturn_t result = IRQ_NONE;
|
|
|
d85c975 |
+ struct bcm2835_host *host = dev_id;
|
|
|
d85c975 |
+ u32 intmask;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ spin_lock(&host->lock);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ intmask = readl(host->ioaddr + SDHSTS);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ writel(SDHSTS_BUSY_IRPT |
|
|
|
d85c975 |
+ SDHSTS_BLOCK_IRPT |
|
|
|
d85c975 |
+ SDHSTS_SDIO_IRPT |
|
|
|
d85c975 |
+ SDHSTS_DATA_FLAG,
|
|
|
d85c975 |
+ host->ioaddr + SDHSTS);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (intmask & SDHSTS_BLOCK_IRPT) {
|
|
|
d85c975 |
+ bcm2835_check_data_error(host, intmask);
|
|
|
d85c975 |
+ host->irq_block = true;
|
|
|
d85c975 |
+ result = IRQ_WAKE_THREAD;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (intmask & SDHSTS_BUSY_IRPT) {
|
|
|
d85c975 |
+ if (!bcm2835_check_cmd_error(host, intmask)) {
|
|
|
d85c975 |
+ host->irq_busy = true;
|
|
|
d85c975 |
+ result = IRQ_WAKE_THREAD;
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ result = IRQ_HANDLED;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* There is no true data interrupt status bit, so it is
|
|
|
d85c975 |
+ * necessary to qualify the data flag with the interrupt
|
|
|
d85c975 |
+ * enable bit.
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+ if ((intmask & SDHSTS_DATA_FLAG) &&
|
|
|
d85c975 |
+ (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
|
|
|
d85c975 |
+ bcm2835_data_irq(host, intmask);
|
|
|
d85c975 |
+ host->irq_data = true;
|
|
|
d85c975 |
+ result = IRQ_WAKE_THREAD;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ spin_unlock(&host->lock);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ return result;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct bcm2835_host *host = dev_id;
|
|
|
d85c975 |
+ unsigned long flags;
|
|
|
d85c975 |
+ bool block, busy, data;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ spin_lock_irqsave(&host->lock, flags);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ block = host->irq_block;
|
|
|
d85c975 |
+ busy = host->irq_busy;
|
|
|
d85c975 |
+ data = host->irq_data;
|
|
|
d85c975 |
+ host->irq_block = false;
|
|
|
d85c975 |
+ host->irq_busy = false;
|
|
|
d85c975 |
+ host->irq_data = false;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ spin_unlock_irqrestore(&host->lock, flags);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_lock(&host->mutex);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (block)
|
|
|
d85c975 |
+ bcm2835_block_irq(host);
|
|
|
d85c975 |
+ if (busy)
|
|
|
d85c975 |
+ bcm2835_busy_irq(host);
|
|
|
d85c975 |
+ if (data)
|
|
|
d85c975 |
+ bcm2835_data_threaded_irq(host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_unlock(&host->mutex);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ return IRQ_HANDLED;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_dma_complete_work(struct work_struct *work)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct bcm2835_host *host =
|
|
|
d85c975 |
+ container_of(work, struct bcm2835_host, dma_work);
|
|
|
d85c975 |
+ struct mmc_data *data = host->data;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_lock(&host->mutex);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->dma_chan) {
|
|
|
d85c975 |
+ dma_unmap_sg(host->dma_chan->device->dev,
|
|
|
d85c975 |
+ data->sg, data->sg_len,
|
|
|
d85c975 |
+ host->dma_dir);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->dma_chan = NULL;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->drain_words) {
|
|
|
d85c975 |
+ unsigned long flags;
|
|
|
d85c975 |
+ void *page;
|
|
|
d85c975 |
+ u32 *buf;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->drain_offset & PAGE_MASK) {
|
|
|
d85c975 |
+ host->drain_page += host->drain_offset >> PAGE_SHIFT;
|
|
|
d85c975 |
+ host->drain_offset &= ~PAGE_MASK;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ local_irq_save(flags);
|
|
|
d85c975 |
+ page = kmap_atomic(host->drain_page);
|
|
|
d85c975 |
+ buf = page + host->drain_offset;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ while (host->drain_words) {
|
|
|
d85c975 |
+ u32 edm = readl(host->ioaddr + SDEDM);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if ((edm >> 4) & 0x1f)
|
|
|
d85c975 |
+ *(buf++) = readl(host->ioaddr + SDDATA);
|
|
|
d85c975 |
+ host->drain_words--;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ kunmap_atomic(page);
|
|
|
d85c975 |
+ local_irq_restore(flags);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ bcm2835_finish_data(host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_unlock(&host->mutex);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ int div;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* The SDCDIV register has 11 bits, and holds (div - 2). But
|
|
|
d85c975 |
+ * in data mode the max is 50MHz wihout a minimum, and only
|
|
|
d85c975 |
+ * the bottom 3 bits are used. Since the switch over is
|
|
|
d85c975 |
+ * automatic (unless we have marked the card as slow...),
|
|
|
d85c975 |
+ * chosen values have to make sense in both modes. Ident mode
|
|
|
d85c975 |
+ * must be 100-400KHz, so can range check the requested
|
|
|
d85c975 |
+ * clock. CMD15 must be used to return to data mode, so this
|
|
|
d85c975 |
+ * can be monitored.
|
|
|
d85c975 |
+ *
|
|
|
d85c975 |
+ * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
|
|
|
d85c975 |
+ * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
|
|
|
d85c975 |
+ *
|
|
|
d85c975 |
+ * 623->400KHz/27.8MHz
|
|
|
d85c975 |
+ * reset value (507)->491159/50MHz
|
|
|
d85c975 |
+ *
|
|
|
d85c975 |
+ * BUT, the 3-bit clock divisor in data mode is too small if
|
|
|
d85c975 |
+ * the core clock is higher than 250MHz, so instead use the
|
|
|
d85c975 |
+ * SLOW_CARD configuration bit to force the use of the ident
|
|
|
d85c975 |
+ * clock divisor at all times.
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (clock < 100000) {
|
|
|
d85c975 |
+ /* Can't stop the clock, but make it as slow as possible
|
|
|
d85c975 |
+ * to show willing
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+ host->cdiv = SDCDIV_MAX_CDIV;
|
|
|
d85c975 |
+ writel(host->cdiv, host->ioaddr + SDCDIV);
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ div = host->max_clk / clock;
|
|
|
d85c975 |
+ if (div < 2)
|
|
|
d85c975 |
+ div = 2;
|
|
|
d85c975 |
+ if ((host->max_clk / div) > clock)
|
|
|
d85c975 |
+ div++;
|
|
|
d85c975 |
+ div -= 2;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (div > SDCDIV_MAX_CDIV)
|
|
|
d85c975 |
+ div = SDCDIV_MAX_CDIV;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ clock = host->max_clk / (div + 2);
|
|
|
d85c975 |
+ host->mmc->actual_clock = clock;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Calibrate some delays */
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->ns_per_fifo_word = (1000000000 / clock) *
|
|
|
d85c975 |
+ ((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->cdiv = div;
|
|
|
d85c975 |
+ writel(host->cdiv, host->ioaddr + SDCDIV);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Set the timeout to 500ms */
|
|
|
d85c975 |
+ writel(host->mmc->actual_clock / 2, host->ioaddr + SDTOUT);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct bcm2835_host *host = mmc_priv(mmc);
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+ u32 edm, fsm;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Reset the error statuses in case this is a retry */
|
|
|
d85c975 |
+ if (mrq->sbc)
|
|
|
d85c975 |
+ mrq->sbc->error = 0;
|
|
|
d85c975 |
+ if (mrq->cmd)
|
|
|
d85c975 |
+ mrq->cmd->error = 0;
|
|
|
d85c975 |
+ if (mrq->data)
|
|
|
d85c975 |
+ mrq->data->error = 0;
|
|
|
d85c975 |
+ if (mrq->stop)
|
|
|
d85c975 |
+ mrq->stop->error = 0;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
|
|
|
d85c975 |
+ dev_err(dev, "unsupported block size (%d bytes)\n",
|
|
|
d85c975 |
+ mrq->data->blksz);
|
|
|
d85c975 |
+ mrq->cmd->error = -EINVAL;
|
|
|
d85c975 |
+ mmc_request_done(mmc, mrq);
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD))
|
|
|
d85c975 |
+ bcm2835_prepare_dma(host, mrq->data);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_lock(&host->mutex);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ WARN_ON(host->mrq);
|
|
|
d85c975 |
+ host->mrq = mrq;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ edm = readl(host->ioaddr + SDEDM);
|
|
|
d85c975 |
+ fsm = edm & SDEDM_FSM_MASK;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if ((fsm != SDEDM_FSM_IDENTMODE) &&
|
|
|
d85c975 |
+ (fsm != SDEDM_FSM_DATAMODE)) {
|
|
|
d85c975 |
+ dev_err(dev, "previous command (%d) not complete (EDM %08x)\n",
|
|
|
d85c975 |
+ readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK,
|
|
|
d85c975 |
+ edm);
|
|
|
d85c975 |
+ bcm2835_dumpregs(host);
|
|
|
d85c975 |
+ mrq->cmd->error = -EILSEQ;
|
|
|
d85c975 |
+ bcm2835_finish_request(host);
|
|
|
d85c975 |
+ mutex_unlock(&host->mutex);
|
|
|
d85c975 |
+ return;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->use_sbc = !!mrq->sbc && (host->mrq->data->flags & MMC_DATA_READ);
|
|
|
d85c975 |
+ if (host->use_sbc) {
|
|
|
d85c975 |
+ if (bcm2835_send_command(host, mrq->sbc)) {
|
|
|
d85c975 |
+ if (!host->use_busy)
|
|
|
d85c975 |
+ bcm2835_finish_command(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+ } else if (bcm2835_send_command(host, mrq->cmd)) {
|
|
|
d85c975 |
+ if (host->data && host->dma_desc) {
|
|
|
d85c975 |
+ /* DMA transfer starts now, PIO starts after irq */
|
|
|
d85c975 |
+ bcm2835_start_dma(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!host->use_busy)
|
|
|
d85c975 |
+ bcm2835_finish_command(host);
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_unlock(&host->mutex);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct bcm2835_host *host = mmc_priv(mmc);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_lock(&host->mutex);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (!ios->clock || ios->clock != host->clock) {
|
|
|
d85c975 |
+ bcm2835_set_clock(host, ios->clock);
|
|
|
d85c975 |
+ host->clock = ios->clock;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* set bus width */
|
|
|
d85c975 |
+ host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
|
|
|
d85c975 |
+ if (ios->bus_width == MMC_BUS_WIDTH_4)
|
|
|
d85c975 |
+ host->hcfg |= SDHCFG_WIDE_EXT_BUS;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->hcfg |= SDHCFG_WIDE_INT_BUS;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Disable clever clock switching, to cope with fast core clocks */
|
|
|
d85c975 |
+ host->hcfg |= SDHCFG_SLOW_CARD;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ writel(host->hcfg, host->ioaddr + SDHCFG);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mutex_unlock(&host->mutex);
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static struct mmc_host_ops bcm2835_ops = {
|
|
|
d85c975 |
+ .request = bcm2835_request,
|
|
|
d85c975 |
+ .set_ios = bcm2835_set_ios,
|
|
|
d85c975 |
+ .hw_reset = bcm2835_reset,
|
|
|
d85c975 |
+};
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static int bcm2835_add_host(struct bcm2835_host *host)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct mmc_host *mmc = host->mmc;
|
|
|
d85c975 |
+ struct device *dev = &host->pdev->dev;
|
|
|
d85c975 |
+ char pio_limit_string[20];
|
|
|
d85c975 |
+ int ret;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mmc->f_max = host->max_clk;
|
|
|
d85c975 |
+ mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n",
|
|
|
d85c975 |
+ mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* host controller capabilities */
|
|
|
d85c975 |
+ mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
|
|
|
d85c975 |
+ MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE |
|
|
|
d85c975 |
+ MMC_CAP_CMD23;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ spin_lock_init(&host->lock);
|
|
|
d85c975 |
+ mutex_init(&host->mutex);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {
|
|
|
d85c975 |
+ dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n");
|
|
|
d85c975 |
+ host->use_dma = false;
|
|
|
d85c975 |
+ } else {
|
|
|
d85c975 |
+ host->use_dma = true;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
d85c975 |
+ host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
d85c975 |
+ host->dma_cfg_tx.slave_id = 13; /* DREQ channel */
|
|
|
d85c975 |
+ host->dma_cfg_tx.direction = DMA_MEM_TO_DEV;
|
|
|
d85c975 |
+ host->dma_cfg_tx.src_addr = 0;
|
|
|
d85c975 |
+ host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
d85c975 |
+ host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
d85c975 |
+ host->dma_cfg_rx.slave_id = 13; /* DREQ channel */
|
|
|
d85c975 |
+ host->dma_cfg_rx.direction = DMA_DEV_TO_MEM;
|
|
|
d85c975 |
+ host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA;
|
|
|
d85c975 |
+ host->dma_cfg_rx.dst_addr = 0;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ if (dmaengine_slave_config(host->dma_chan_rxtx,
|
|
|
d85c975 |
+ &host->dma_cfg_tx) != 0 ||
|
|
|
d85c975 |
+ dmaengine_slave_config(host->dma_chan_rxtx,
|
|
|
d85c975 |
+ &host->dma_cfg_rx) != 0)
|
|
|
d85c975 |
+ host->use_dma = false;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mmc->max_segs = 128;
|
|
|
d85c975 |
+ mmc->max_req_size = 524288;
|
|
|
d85c975 |
+ mmc->max_seg_size = mmc->max_req_size;
|
|
|
d85c975 |
+ mmc->max_blk_size = 1024;
|
|
|
d85c975 |
+ mmc->max_blk_count = 65535;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* report supported voltage ranges */
|
|
|
d85c975 |
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ INIT_WORK(&host->dma_work, bcm2835_dma_complete_work);
|
|
|
d85c975 |
+ INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Set interrupt enables */
|
|
|
d85c975 |
+ host->hcfg = SDHCFG_BUSY_IRPT_EN;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ bcm2835_reset_internal(host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ ret = request_threaded_irq(host->irq, bcm2835_irq,
|
|
|
d85c975 |
+ bcm2835_threaded_irq,
|
|
|
d85c975 |
+ 0, mmc_hostname(mmc), host);
|
|
|
d85c975 |
+ if (ret) {
|
|
|
d85c975 |
+ dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret);
|
|
|
d85c975 |
+ return ret;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ ret = mmc_add_host(mmc);
|
|
|
d85c975 |
+ if (ret) {
|
|
|
d85c975 |
+ free_irq(host->irq, host);
|
|
|
d85c975 |
+ return ret;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ pio_limit_string[0] = '\0';
|
|
|
d85c975 |
+ if (host->use_dma && (PIO_THRESHOLD > 0))
|
|
|
d85c975 |
+ sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD);
|
|
|
d85c975 |
+ dev_info(dev, "loaded - DMA %s%s\n",
|
|
|
d85c975 |
+ host->use_dma ? "enabled" : "disabled", pio_limit_string);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ return 0;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static int bcm2835_probe(struct platform_device *pdev)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct device *dev = &pdev->dev;
|
|
|
d85c975 |
+ struct clk *clk;
|
|
|
d85c975 |
+ struct resource *iomem;
|
|
|
d85c975 |
+ struct bcm2835_host *host;
|
|
|
d85c975 |
+ struct mmc_host *mmc;
|
|
|
d85c975 |
+ const __be32 *regaddr_p;
|
|
|
d85c975 |
+ int ret;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ dev_dbg(dev, "%s\n", __func__);
|
|
|
d85c975 |
+ mmc = mmc_alloc_host(sizeof(*host), dev);
|
|
|
d85c975 |
+ if (!mmc)
|
|
|
d85c975 |
+ return -ENOMEM;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mmc->ops = &bcm2835_ops;
|
|
|
d85c975 |
+ host = mmc_priv(mmc);
|
|
|
d85c975 |
+ host->mmc = mmc;
|
|
|
d85c975 |
+ host->pdev = pdev;
|
|
|
d85c975 |
+ spin_lock_init(&host->lock);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
d85c975 |
+ host->ioaddr = devm_ioremap_resource(dev, iomem);
|
|
|
d85c975 |
+ if (IS_ERR(host->ioaddr)) {
|
|
|
d85c975 |
+ ret = PTR_ERR(host->ioaddr);
|
|
|
d85c975 |
+ goto err;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ /* Parse OF address directly to get the physical address for
|
|
|
d85c975 |
+ * DMA to our registers.
|
|
|
d85c975 |
+ */
|
|
|
d85c975 |
+ regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
|
|
|
d85c975 |
+ if (!regaddr_p) {
|
|
|
d85c975 |
+ dev_err(dev, "Can't get phys address\n");
|
|
|
d85c975 |
+ ret = -EINVAL;
|
|
|
d85c975 |
+ goto err;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->phys_addr = be32_to_cpup(regaddr_p);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->dma_chan = NULL;
|
|
|
d85c975 |
+ host->dma_desc = NULL;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx");
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ clk = devm_clk_get(dev, NULL);
|
|
|
d85c975 |
+ if (IS_ERR(clk)) {
|
|
|
d85c975 |
+ ret = PTR_ERR(clk);
|
|
|
d85c975 |
+ if (ret != -EPROBE_DEFER)
|
|
|
d85c975 |
+ dev_err(dev, "could not get clk: %d\n", ret);
|
|
|
d85c975 |
+ goto err;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->max_clk = clk_get_rate(clk);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ host->irq = platform_get_irq(pdev, 0);
|
|
|
d85c975 |
+ if (host->irq <= 0) {
|
|
|
d85c975 |
+ dev_err(dev, "get IRQ failed\n");
|
|
|
d85c975 |
+ ret = -EINVAL;
|
|
|
d85c975 |
+ goto err;
|
|
|
d85c975 |
+ }
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ ret = mmc_of_parse(mmc);
|
|
|
d85c975 |
+ if (ret)
|
|
|
d85c975 |
+ goto err;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ ret = bcm2835_add_host(host);
|
|
|
d85c975 |
+ if (ret)
|
|
|
d85c975 |
+ goto err;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ platform_set_drvdata(pdev, host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ dev_dbg(dev, "%s -> OK\n", __func__);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ return 0;
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+err:
|
|
|
d85c975 |
+ dev_dbg(dev, "%s -> err %d\n", __func__, ret);
|
|
|
d85c975 |
+ mmc_free_host(mmc);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ return ret;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static int bcm2835_remove(struct platform_device *pdev)
|
|
|
d85c975 |
+{
|
|
|
d85c975 |
+ struct bcm2835_host *host = platform_get_drvdata(pdev);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mmc_remove_host(host->mmc);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ free_irq(host->irq, host);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ cancel_work_sync(&host->dma_work);
|
|
|
d85c975 |
+ cancel_delayed_work_sync(&host->timeout_work);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ mmc_free_host(host->mmc);
|
|
|
d85c975 |
+ platform_set_drvdata(pdev, NULL);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+ return 0;
|
|
|
d85c975 |
+}
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static const struct of_device_id bcm2835_match[] = {
|
|
|
d85c975 |
+ { .compatible = "brcm,bcm2835-sdhost" },
|
|
|
d85c975 |
+ { }
|
|
|
d85c975 |
+};
|
|
|
d85c975 |
+MODULE_DEVICE_TABLE(of, bcm2835_match);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+static struct platform_driver bcm2835_driver = {
|
|
|
d85c975 |
+ .probe = bcm2835_probe,
|
|
|
d85c975 |
+ .remove = bcm2835_remove,
|
|
|
d85c975 |
+ .driver = {
|
|
|
d85c975 |
+ .name = "sdhost-bcm2835",
|
|
|
d85c975 |
+ .of_match_table = bcm2835_match,
|
|
|
d85c975 |
+ },
|
|
|
d85c975 |
+};
|
|
|
d85c975 |
+module_platform_driver(bcm2835_driver);
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+MODULE_ALIAS("platform:sdhost-bcm2835");
|
|
|
d85c975 |
+MODULE_DESCRIPTION("BCM2835 SDHost driver");
|
|
|
d85c975 |
+MODULE_LICENSE("GPL v2");
|
|
|
d85c975 |
+MODULE_AUTHOR("Phil Elwell");
|
|
|
d85c975 |
From patchwork Wed Mar 8 09:19:05 2017
|
|
|
d85c975 |
Content-Type: text/plain; charset="utf-8"
|
|
|
d85c975 |
MIME-Version: 1.0
|
|
|
d85c975 |
Content-Transfer-Encoding: 7bit
|
|
|
d85c975 |
Subject: [v4,3/7] mmc: bcm2835: add sdhost controller to devicetree
|
|
|
d85c975 |
From: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
X-Patchwork-Id: 9610693
|
|
|
d85c975 |
Message-Id: <1488964751-22763-6-git-send-email-kraxel@redhat.com>
|
|
|
d85c975 |
To: linux-rpi-kernel@lists.infradead.org
|
|
|
d85c975 |
Cc: mark.rutland@arm.com, stefan.wahren@i2se.com, ulf.hansson@linaro.org,
|
|
|
d85c975 |
f.fainelli@gmail.com, sbranden@broadcom.com, devicetree@vger.kernel.org,
|
|
|
d85c975 |
rjui@broadcom.com, lee@kernel.org, will.deacon@arm.com,
|
|
|
d85c975 |
linux@armlinux.org.uk,
|
|
|
d85c975 |
linux-kernel@vger.kernel.org, eric@anholt.net, robh+dt@kernel.org,
|
|
|
d85c975 |
bcm-kernel-feedback-list@broadcom.com, Gerd Hoffmann <kraxel@redhat.com>,
|
|
|
d85c975 |
catalin.marinas@arm.com, linux-mmc@vger.kernel.org,
|
|
|
d85c975 |
linux-arm-kernel@lists.infradead.org
|
|
|
d85c975 |
Date: Wed, 8 Mar 2017 10:19:05 +0100
|
|
|
d85c975 |
|
|
|
d85c975 |
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
Acked-by: Eric Anholt <eric@anholt.net>
|
|
|
d85c975 |
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
|
|
|
d85c975 |
---
|
|
|
d85c975 |
arch/arm/boot/dts/bcm2835-rpi.dtsi | 6 ++++++
|
|
|
d85c975 |
arch/arm/boot/dts/bcm283x.dtsi | 10 ++++++++++
|
|
|
d85c975 |
2 files changed, 16 insertions(+)
|
|
|
d85c975 |
|
|
|
d85c975 |
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
|
|
|
d85c975 |
index 1e00a28..8b95832 100644
|
|
|
d85c975 |
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
|
|
|
d85c975 |
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
|
|
|
d85c975 |
@@ -69,6 +69,12 @@
|
|
|
d85c975 |
bus-width = <4>;
|
|
|
d85c975 |
};
|
|
|
d85c975 |
|
|
|
d85c975 |
+&sdhost {
|
|
|
d85c975 |
+ pinctrl-names = "default";
|
|
|
d85c975 |
+ pinctrl-0 = <&sdhost_gpio48>;
|
|
|
d85c975 |
+ bus-width = <4>;
|
|
|
d85c975 |
+};
|
|
|
d85c975 |
+
|
|
|
d85c975 |
&pwm {
|
|
|
d85c975 |
pinctrl-names = "default";
|
|
|
d85c975 |
pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>;
|
|
|
d85c975 |
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
|
|
|
d85c975 |
index 9798bc9..19099a5 100644
|
|
|
d85c975 |
--- a/arch/arm/boot/dts/bcm283x.dtsi
|
|
|
d85c975 |
+++ b/arch/arm/boot/dts/bcm283x.dtsi
|
|
|
d85c975 |
@@ -350,6 +350,16 @@
|
|
|
d85c975 |
arm,primecell-periphid = <0x00241011>;
|
|
|
d85c975 |
};
|
|
|
d85c975 |
|
|
|
d85c975 |
+ sdhost: mmc@7e202000 {
|
|
|
d85c975 |
+ compatible = "brcm,bcm2835-sdhost";
|
|
|
d85c975 |
+ reg = <0x7e202000 0x100>;
|
|
|
d85c975 |
+ interrupts = <2 24>;
|
|
|
d85c975 |
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
|
d85c975 |
+ dmas = <&dma 13>;
|
|
|
d85c975 |
+ dma-names = "rx-tx";
|
|
|
d85c975 |
+ status = "disabled";
|
|
|
d85c975 |
+ };
|
|
|
d85c975 |
+
|
|
|
d85c975 |
i2s: i2s@7e203000 {
|
|
|
d85c975 |
compatible = "brcm,bcm2835-i2s";
|
|
|
d85c975 |
reg = <0x7e203000 0x20>,
|
|
|
d85c975 |
From patchwork Wed Mar 8 09:19:07 2017
|
|
|
d85c975 |
Content-Type: text/plain; charset="utf-8"
|
|
|
d85c975 |
MIME-Version: 1.0
|
|
|
d85c975 |
Content-Transfer-Encoding: 7bit
|
|
|
d85c975 |
Subject: [v4, 4/7] arm: set CONFIG_MMC_BCM2835=y in bcm2835_defconfig and
|
|
|
d85c975 |
multi_v7_defconfig
|
|
|
d85c975 |
From: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
X-Patchwork-Id: 9610689
|
|
|
d85c975 |
Message-Id: <1488964751-22763-8-git-send-email-kraxel@redhat.com>
|
|
|
d85c975 |
To: linux-rpi-kernel@lists.infradead.org
|
|
|
d85c975 |
Cc: mark.rutland@arm.com, stefan.wahren@i2se.com, ulf.hansson@linaro.org,
|
|
|
d85c975 |
f.fainelli@gmail.com, sbranden@broadcom.com, devicetree@vger.kernel.org,
|
|
|
d85c975 |
rjui@broadcom.com, lee@kernel.org, will.deacon@arm.com,
|
|
|
d85c975 |
linux@armlinux.org.uk,
|
|
|
d85c975 |
linux-kernel@vger.kernel.org, eric@anholt.net, robh+dt@kernel.org,
|
|
|
d85c975 |
bcm-kernel-feedback-list@broadcom.com, Gerd Hoffmann <kraxel@redhat.com>,
|
|
|
d85c975 |
catalin.marinas@arm.com, linux-mmc@vger.kernel.org,
|
|
|
d85c975 |
linux-arm-kernel@lists.infradead.org
|
|
|
d85c975 |
Date: Wed, 8 Mar 2017 10:19:07 +0100
|
|
|
d85c975 |
|
|
|
d85c975 |
We need to enable this controller so that we can switch the SD card's
|
|
|
d85c975 |
pinmux over to it by default, which will improve storage performance.
|
|
|
d85c975 |
|
|
|
d85c975 |
Read access (dd with 64k blocks on rpi2):
|
|
|
d85c975 |
CONFIG_MMC_SDHCI_IPROC: 11-12 MB/s
|
|
|
d85c975 |
CONFIG_MMC_BCM2835: 19-20 MB/s
|
|
|
d85c975 |
|
|
|
d85c975 |
Differences on write access are pretty much in the noise.
|
|
|
d85c975 |
|
|
|
d85c975 |
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
---
|
|
|
d85c975 |
arch/arm/configs/bcm2835_defconfig | 1 +
|
|
|
d85c975 |
arch/arm/configs/multi_v7_defconfig | 1 +
|
|
|
d85c975 |
2 files changed, 2 insertions(+)
|
|
|
d85c975 |
|
|
|
d85c975 |
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
|
|
|
d85c975 |
index 4b89f4e..3767c24 100644
|
|
|
d85c975 |
--- a/arch/arm/configs/bcm2835_defconfig
|
|
|
d85c975 |
+++ b/arch/arm/configs/bcm2835_defconfig
|
|
|
d85c975 |
@@ -92,6 +92,7 @@ CONFIG_MMC=y
|
|
|
d85c975 |
CONFIG_MMC_SDHCI=y
|
|
|
d85c975 |
CONFIG_MMC_SDHCI_PLTFM=y
|
|
|
d85c975 |
CONFIG_MMC_SDHCI_IPROC=y
|
|
|
d85c975 |
+CONFIG_MMC_BCM2835=y
|
|
|
d85c975 |
CONFIG_NEW_LEDS=y
|
|
|
d85c975 |
CONFIG_LEDS_CLASS=y
|
|
|
d85c975 |
CONFIG_LEDS_GPIO=y
|
|
|
d85c975 |
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
|
|
|
d85c975 |
index a94126f..63b94d0 100644
|
|
|
d85c975 |
--- a/arch/arm/configs/multi_v7_defconfig
|
|
|
d85c975 |
+++ b/arch/arm/configs/multi_v7_defconfig
|
|
|
d85c975 |
@@ -730,6 +730,7 @@ CONFIG_MMC_DW_EXYNOS=y
|
|
|
d85c975 |
CONFIG_MMC_DW_ROCKCHIP=y
|
|
|
d85c975 |
CONFIG_MMC_SH_MMCIF=y
|
|
|
d85c975 |
CONFIG_MMC_SUNXI=y
|
|
|
d85c975 |
+CONFIG_MMC_BCM2835=y
|
|
|
d85c975 |
CONFIG_NEW_LEDS=y
|
|
|
d85c975 |
CONFIG_LEDS_CLASS=y
|
|
|
d85c975 |
CONFIG_LEDS_CLASS_FLASH=m
|
|
|
d85c975 |
From patchwork Wed Mar 8 09:19:09 2017
|
|
|
d85c975 |
Content-Type: text/plain; charset="utf-8"
|
|
|
d85c975 |
MIME-Version: 1.0
|
|
|
d85c975 |
Content-Transfer-Encoding: 7bit
|
|
|
d85c975 |
Subject: [v4,5/7] arm64: set CONFIG_MMC_BCM2835=y in defconfig
|
|
|
d85c975 |
From: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
X-Patchwork-Id: 9610647
|
|
|
d85c975 |
Message-Id: <1488964751-22763-10-git-send-email-kraxel@redhat.com>
|
|
|
d85c975 |
To: linux-rpi-kernel@lists.infradead.org
|
|
|
d85c975 |
Cc: mark.rutland@arm.com, stefan.wahren@i2se.com, ulf.hansson@linaro.org,
|
|
|
d85c975 |
f.fainelli@gmail.com, sbranden@broadcom.com, devicetree@vger.kernel.org,
|
|
|
d85c975 |
rjui@broadcom.com, lee@kernel.org, will.deacon@arm.com,
|
|
|
d85c975 |
linux@armlinux.org.uk,
|
|
|
d85c975 |
linux-kernel@vger.kernel.org, eric@anholt.net, robh+dt@kernel.org,
|
|
|
d85c975 |
bcm-kernel-feedback-list@broadcom.com, Gerd Hoffmann <kraxel@redhat.com>,
|
|
|
d85c975 |
catalin.marinas@arm.com, linux-mmc@vger.kernel.org,
|
|
|
d85c975 |
linux-arm-kernel@lists.infradead.org
|
|
|
d85c975 |
Date: Wed, 8 Mar 2017 10:19:09 +0100
|
|
|
d85c975 |
|
|
|
d85c975 |
We need to enable this controller so that we can switch the SD card's
|
|
|
d85c975 |
pinmux over to it by default, which will improve storage performance.
|
|
|
d85c975 |
|
|
|
d85c975 |
Read access (dd with 64k blocks on rpi2):
|
|
|
d85c975 |
CONFIG_MMC_SDHCI_IPROC: 11-12 MB/s
|
|
|
d85c975 |
CONFIG_MMC_BCM2835: 19-20 MB/s
|
|
|
d85c975 |
|
|
|
d85c975 |
Differences on write access are pretty much in the noise.
|
|
|
d85c975 |
|
|
|
d85c975 |
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
---
|
|
|
d85c975 |
arch/arm64/configs/defconfig | 1 +
|
|
|
d85c975 |
1 file changed, 1 insertion(+)
|
|
|
d85c975 |
|
|
|
d85c975 |
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
|
|
|
d85c975 |
index 7c48028..519a55c 100644
|
|
|
d85c975 |
--- a/arch/arm64/configs/defconfig
|
|
|
d85c975 |
+++ b/arch/arm64/configs/defconfig
|
|
|
d85c975 |
@@ -398,6 +398,7 @@ CONFIG_MMC_DW_EXYNOS=y
|
|
|
d85c975 |
CONFIG_MMC_DW_K3=y
|
|
|
d85c975 |
CONFIG_MMC_DW_ROCKCHIP=y
|
|
|
d85c975 |
CONFIG_MMC_SUNXI=y
|
|
|
d85c975 |
+CONFIG_MMC_BCM2835=y
|
|
|
d85c975 |
CONFIG_NEW_LEDS=y
|
|
|
d85c975 |
CONFIG_LEDS_CLASS=y
|
|
|
d85c975 |
CONFIG_LEDS_GPIO=y
|
|
|
d85c975 |
From patchwork Wed Mar 8 09:19:10 2017
|
|
|
d85c975 |
Content-Type: text/plain; charset="utf-8"
|
|
|
d85c975 |
MIME-Version: 1.0
|
|
|
d85c975 |
Content-Transfer-Encoding: 7bit
|
|
|
d85c975 |
Subject: [v4,6/7] arm: dts: bcm283x: switch from &sdhci to &sdhost
|
|
|
d85c975 |
From: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
X-Patchwork-Id: 9610687
|
|
|
d85c975 |
Message-Id: <1488964751-22763-11-git-send-email-kraxel@redhat.com>
|
|
|
d85c975 |
To: linux-rpi-kernel@lists.infradead.org
|
|
|
d85c975 |
Cc: mark.rutland@arm.com, stefan.wahren@i2se.com, ulf.hansson@linaro.org,
|
|
|
d85c975 |
f.fainelli@gmail.com, sbranden@broadcom.com, devicetree@vger.kernel.org,
|
|
|
d85c975 |
rjui@broadcom.com, lee@kernel.org, will.deacon@arm.com,
|
|
|
d85c975 |
linux@armlinux.org.uk,
|
|
|
d85c975 |
linux-kernel@vger.kernel.org, eric@anholt.net, robh+dt@kernel.org,
|
|
|
d85c975 |
bcm-kernel-feedback-list@broadcom.com, Gerd Hoffmann <kraxel@redhat.com>,
|
|
|
d85c975 |
catalin.marinas@arm.com, linux-mmc@vger.kernel.org,
|
|
|
d85c975 |
linux-arm-kernel@lists.infradead.org
|
|
|
d85c975 |
Date: Wed, 8 Mar 2017 10:19:10 +0100
|
|
|
d85c975 |
|
|
|
d85c975 |
sdcard access with the sdhost controller is faster.
|
|
|
d85c975 |
|
|
|
d85c975 |
Read access (dd with 64k blocks on rpi2):
|
|
|
d85c975 |
CONFIG_MMC_SDHCI_IPROC: 11-12 MB/s
|
|
|
d85c975 |
CONFIG_MMC_BCM2835: 19-20 MB/s
|
|
|
d85c975 |
|
|
|
d85c975 |
Differences on write access are pretty much in the noise.
|
|
|
d85c975 |
|
|
|
d85c975 |
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
Acked-by: Eric Anholt <eric@anholt.net>
|
|
|
d85c975 |
---
|
|
|
d85c975 |
arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 +-
|
|
|
d85c975 |
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
d85c975 |
|
|
|
d85c975 |
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
|
|
|
d85c975 |
index 8b95832..e36c392 100644
|
|
|
d85c975 |
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
|
|
|
d85c975 |
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
|
|
|
d85c975 |
@@ -65,13 +65,13 @@
|
|
|
d85c975 |
&sdhci {
|
|
|
d85c975 |
pinctrl-names = "default";
|
|
|
d85c975 |
pinctrl-0 = <&emmc_gpio48>;
|
|
|
d85c975 |
- status = "okay";
|
|
|
d85c975 |
bus-width = <4>;
|
|
|
d85c975 |
};
|
|
|
d85c975 |
|
|
|
d85c975 |
&sdhost {
|
|
|
d85c975 |
pinctrl-names = "default";
|
|
|
d85c975 |
pinctrl-0 = <&sdhost_gpio48>;
|
|
|
d85c975 |
+ status = "okay";
|
|
|
d85c975 |
bus-width = <4>;
|
|
|
d85c975 |
};
|
|
|
d85c975 |
|
|
|
d85c975 |
From patchwork Wed Mar 8 09:19:11 2017
|
|
|
d85c975 |
Content-Type: text/plain; charset="utf-8"
|
|
|
d85c975 |
MIME-Version: 1.0
|
|
|
d85c975 |
Content-Transfer-Encoding: 7bit
|
|
|
d85c975 |
Subject: [v4,7/7] arm64: dts: bcm2837: add &sdhci and &sdhost
|
|
|
d85c975 |
From: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
X-Patchwork-Id: 9610637
|
|
|
d85c975 |
Message-Id: <1488964751-22763-12-git-send-email-kraxel@redhat.com>
|
|
|
d85c975 |
To: linux-rpi-kernel@lists.infradead.org
|
|
|
d85c975 |
Cc: mark.rutland@arm.com, stefan.wahren@i2se.com, ulf.hansson@linaro.org,
|
|
|
d85c975 |
f.fainelli@gmail.com, sbranden@broadcom.com, devicetree@vger.kernel.org,
|
|
|
d85c975 |
rjui@broadcom.com, lee@kernel.org, will.deacon@arm.com,
|
|
|
d85c975 |
linux@armlinux.org.uk,
|
|
|
d85c975 |
linux-kernel@vger.kernel.org, eric@anholt.net, robh+dt@kernel.org,
|
|
|
d85c975 |
bcm-kernel-feedback-list@broadcom.com, Gerd Hoffmann <kraxel@redhat.com>,
|
|
|
d85c975 |
catalin.marinas@arm.com, linux-mmc@vger.kernel.org,
|
|
|
d85c975 |
linux-arm-kernel@lists.infradead.org
|
|
|
d85c975 |
Date: Wed, 8 Mar 2017 10:19:11 +0100
|
|
|
d85c975 |
|
|
|
d85c975 |
For the raspberry pi 3 we'll need both sdhci (handles sdio wifi) and
|
|
|
d85c975 |
sdhost (handles sdcard).
|
|
|
d85c975 |
|
|
|
d85c975 |
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
d85c975 |
Acked-by: Eric Anholt <eric@anholt.net>
|
|
|
d85c975 |
---
|
|
|
d85c975 |
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts | 17 +++++++++++++++++
|
|
|
d85c975 |
1 file changed, 17 insertions(+)
|
|
|
d85c975 |
|
|
|
d85c975 |
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
|
|
|
d85c975 |
index c309633..972f14d 100644
|
|
|
d85c975 |
--- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
|
|
|
d85c975 |
+++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
|
|
|
d85c975 |
@@ -22,3 +22,20 @@
|
|
|
d85c975 |
&uart1 {
|
|
|
d85c975 |
status = "okay";
|
|
|
d85c975 |
};
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+/* SDHCI is used to control the SDIO for wireless */
|
|
|
d85c975 |
+&sdhci {
|
|
|
d85c975 |
+ pinctrl-names = "default";
|
|
|
d85c975 |
+ pinctrl-0 = <&emmc_gpio34>;
|
|
|
d85c975 |
+ status = "okay";
|
|
|
d85c975 |
+ bus-width = <4>;
|
|
|
d85c975 |
+ non-removable;
|
|
|
d85c975 |
+};
|
|
|
d85c975 |
+
|
|
|
d85c975 |
+/* SDHOST is used to drive the SD card */
|
|
|
d85c975 |
+&sdhost {
|
|
|
d85c975 |
+ pinctrl-names = "default";
|
|
|
d85c975 |
+ pinctrl-0 = <&sdhost_gpio48>;
|
|
|
d85c975 |
+ status = "okay";
|
|
|
d85c975 |
+ bus-width = <4>;
|
|
|
d85c975 |
+};
|