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From d40a5938a10a3ba73bce6395729fefd8b8bb1c07 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Thu, 29 Jun 2017 10:05:05 +0100
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Subject: [PATCH] drm/vc4: Fix VBLANK handling in crtc->enable() path
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When we are enabling a CRTC, drm_crtc_vblank_get() is called before
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drm_crtc_vblank_on(), which is not supposed to happen (hence the
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WARN_ON() in the code). To solve the problem, we delay the 'update
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display list' operation after the CRTC is actually enabled.
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Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 66 +++++++++++++++++++++++++++---------------
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1 file changed, 43 insertions(+), 23 deletions(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
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index d86c8cce3182..316bd6210d69 100644
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -530,6 +530,34 @@ static void vc4_crtc_disable(struct drm_crtc *crtc)
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SCALER_DISPSTATX_EMPTY);
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}
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+static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
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+{
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+ struct drm_device *dev = crtc->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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+ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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+
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+ if (crtc->state->event) {
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+ unsigned long flags;
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+
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+ crtc->state->event->pipe = drm_crtc_index(crtc);
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+
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+ WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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+
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+ spin_lock_irqsave(&dev->event_lock, flags);
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+ vc4_crtc->event = crtc->state->event;
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+ crtc->state->event = NULL;
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+
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+ HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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+ vc4_state->mm.start);
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+
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+ spin_unlock_irqrestore(&dev->event_lock, flags);
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+ } else {
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+ HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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+ vc4_state->mm.start);
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+ }
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+}
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+
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static void vc4_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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@@ -540,6 +568,12 @@ static void vc4_crtc_enable(struct drm_crtc *crtc)
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require_hvs_enabled(dev);
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+ /* Enable vblank irq handling before crtc is started otherwise
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+ * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
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+ */
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+ drm_crtc_vblank_on(crtc);
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+ vc4_crtc_update_dlist(crtc);
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+
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/* Turn on the scaler, which will wait for vstart to start
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* compositing.
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*/
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@@ -551,9 +585,6 @@ static void vc4_crtc_enable(struct drm_crtc *crtc)
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/* Turn on the pixel valve, which will emit the vstart signal. */
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CRTC_WRITE(PV_V_CONTROL,
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CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
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-
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- /* Enable vblank irq handling after crtc is started. */
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- drm_crtc_vblank_on(crtc);
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}
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static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
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@@ -608,7 +639,6 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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struct drm_plane *plane;
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bool debug_dump_regs = false;
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@@ -630,25 +660,15 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
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WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
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- if (crtc->state->event) {
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- unsigned long flags;
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-
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- crtc->state->event->pipe = drm_crtc_index(crtc);
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-
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- WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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-
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- spin_lock_irqsave(&dev->event_lock, flags);
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- vc4_crtc->event = crtc->state->event;
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- crtc->state->event = NULL;
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-
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- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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- vc4_state->mm.start);
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-
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- spin_unlock_irqrestore(&dev->event_lock, flags);
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- } else {
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- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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- vc4_state->mm.start);
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- }
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+ /* Only update DISPLIST if the CRTC was already running and is not
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+ * being disabled.
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+ * vc4_crtc_enable() takes care of updating the dlist just after
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+ * re-enabling VBLANK interrupts and before enabling the engine.
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+ * If the CRTC is being disabled, there's no point in updating this
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+ * information.
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+ */
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+ if (crtc->state->active && old_state->active)
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+ vc4_crtc_update_dlist(crtc);
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
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--
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2.13.0
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