From 927eaa238f895a83cae3157a176086c4337e0533 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Aug 02 2016 20:05:05 +0000 Subject: Sync 2 skylake i915 bug-fix patches with latest upstream version --- diff --git a/Revert-ALSA-hda-remove-controller-dependency-on-i915.patch b/Revert-ALSA-hda-remove-controller-dependency-on-i915.patch deleted file mode 100644 index 657f7aa..0000000 --- a/Revert-ALSA-hda-remove-controller-dependency-on-i915.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 89b9366047f51fcef7f7e36f2b351a98326c8656 Mon Sep 17 00:00:00 2001 -From: Hans de Goede -Date: Tue, 12 Jul 2016 22:40:01 +0200 -Subject: [PATCH] Revert "ALSA: hda - remove controller dependency on i915 - power well for SKL" - -This reverts commit 03b135cebc47d75ea2dc346770374ab741966955. ---- - sound/pci/hda/hda_intel.c | 4 +++- - sound/pci/hda/patch_hdmi.c | 2 +- - 2 files changed, 4 insertions(+), 2 deletions(-) - -diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c -index e320c44..290d60f 100644 ---- a/sound/pci/hda/hda_intel.c -+++ b/sound/pci/hda/hda_intel.c -@@ -361,7 +361,9 @@ enum { - #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ - ((pci)->device == 0x0c0c) || \ - ((pci)->device == 0x0d0c) || \ -- ((pci)->device == 0x160c)) -+ ((pci)->device == 0x160c) || \ -+ ((pci)->device == 0xa170) || \ -+ ((pci)->device == 0x9d70)) - - #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170) - #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70) -diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c -index d0d5ad8..9203da1 100644 ---- a/sound/pci/hda/patch_hdmi.c -+++ b/sound/pci/hda/patch_hdmi.c -@@ -2379,7 +2379,7 @@ static int patch_i915_hsw_hdmi(struct hda_codec *codec) - /* For Haswell/Broadwell, the controller is also in the power well and - * can cover the codec power request, and so need not set this flag. - */ -- if (!is_haswell(codec) && !is_broadwell(codec)) -+ if (!is_haswell(codec) && !is_broadwell(codec) && !is_skylake(codec)) - codec->core.link_power_control = 1; - - codec->patch_ops.set_power_state = haswell_set_power_state; --- -2.7.4 - diff --git a/drm-i915-Acquire-audio-powerwell-for-HD-Audio-regist.patch b/drm-i915-Acquire-audio-powerwell-for-HD-Audio-regist.patch new file mode 100644 index 0000000..a5dc6f3 --- /dev/null +++ b/drm-i915-Acquire-audio-powerwell-for-HD-Audio-regist.patch @@ -0,0 +1,64 @@ +From 74f829a6e44fe217b6161f8935524fc807be0648 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Sat, 9 Jul 2016 11:01:20 +0100 +Subject: [PATCH] drm/i915: Acquire audio powerwell for HD-Audio registers + +On Haswell/Broadwell, the HD-Audio block is inside the HDMI/display +power well and so the sna-hda audio codec acquires the display power +well while it is operational. However, Skylake separates the powerwells +again, but yet we still need the audio powerwell to setup the registers. +(But then the hardware uses those registers even while powered off???) + +v2: Grab both rpm wakelock and audio wakelock + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96214 +Fixes: 03b135cebc47 "ALSA: hda - remove dependency on i915 power well for SKL") +Signed-off-by: Chris Wilson +Cc: Libin Yang +Cc: Takashi Iwai +Cc: Marius Vlad +--- + drivers/gpu/drm/i915/intel_audio.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c +index 5d5f6bc10e85..948a7a52e3f8 100644 +--- a/drivers/gpu/drm/i915/intel_audio.c ++++ b/drivers/gpu/drm/i915/intel_audio.c +@@ -600,6 +600,8 @@ static void i915_audio_component_codec_wake_override(struct device *dev, + if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) + return; + ++ i915_audio_component_get_power(dev); ++ + /* + * Enable/disable generating the codec wake signal, overriding the + * internal logic to generate the codec wake to controller. +@@ -615,6 +617,8 @@ static void i915_audio_component_codec_wake_override(struct device *dev, + I915_WRITE(HSW_AUD_CHICKENBIT, tmp); + usleep_range(1000, 1500); + } ++ ++ i915_audio_component_put_power(dev); + } + + /* Get CDCLK in kHz */ +@@ -648,6 +652,7 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, + !IS_HASWELL(dev_priv)) + return 0; + ++ i915_audio_component_get_power(dev); + mutex_lock(&dev_priv->av_mutex); + /* 1. get the pipe */ + intel_encoder = dev_priv->dig_port_map[port]; +@@ -698,6 +703,7 @@ static int i915_audio_component_sync_audio_rate(struct device *dev, + + unlock: + mutex_unlock(&dev_priv->av_mutex); ++ i915_audio_component_put_power(dev); + return err; + } + +-- +2.8.1 + diff --git a/drm-i915-skl-Add-support-for-the-SAGV-fix-underrun-hangs.patch b/drm-i915-skl-Add-support-for-the-SAGV-fix-underrun-hangs.patch deleted file mode 100644 index 2735f25..0000000 --- a/drm-i915-skl-Add-support-for-the-SAGV-fix-underrun-hangs.patch +++ /dev/null @@ -1,230 +0,0 @@ -From 75ec12176f3ae89ed2ccf35ae675cf605970d2fa Mon Sep 17 00:00:00 2001 -From: "cpaul@redhat.com" -Date: Tue, 12 Jul 2016 13:36:03 -0400 -Subject: [PATCH] drm/i915/skl: Add support for the SAGV, fix underrun hangs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Since the watermark calculations for Skylake are still broken, we're apt -to hitting underruns very easily under multi-monitor configurations. -While it would be lovely if this was fixed, it's not. Another problem -that's been coming from this however, is the mysterious issue of -underruns causing full system hangs. An easy way to reproduce this with -a skylake system: - -- Get a laptop with a skylake GPU, and hook up two external monitors to - it -- Move the cursor from the built-in LCD to one of the external displays - as quickly as you can -- You'll get a few pipe underruns, and eventually the entire system will - just freeze. - -After doing a lot of investigation and reading through the bspec, I -found the existence of the SAGV, which is responsible for adjusting the -system agent voltage and clock frequencies depending on how much power -we need. According to the bspec: - -"The display engine access to system memory is blocked during the - adjustment time. SAGV defaults to enabled. Software must use the - GT-driver pcode mailbox to disable SAGV when the display engine is not - able to tolerate the blocking time." - -The rest of the bspec goes on to explain that software can simply leave -the SAGV enabled, and disable it when we use interlaced pipes/have more -then one pipe active. - -Sure enough, with this patchset the system hangs resulting from pipe -underruns on Skylake have completely vanished on my T460s. Additionally, -the bspec mentions turning off the SAGV with more then one pipe enabled -as a workaround for display underruns. While this patch doesn't entirely -fix that, it looks like it does improve the situation a little bit so -it's likely this is going to be required to make watermarks on Skylake -fully functional. - -Changes since v2: - - Really apply minor style nitpicks to patch this time -Changes since v1: - - Added comments about this probably being one of the requirements to - fixing Skylake's watermark issues - - Minor style nitpicks from Matt Roper - - Disable these functions on Broxton, since it doesn't have an SAGV - -Cc: Matt Roper -Cc: Daniel Vetter -Cc: Ville Syrjälä -Signed-off-by: Lyude -Reviewed-by: Matt Roper ---- - drivers/gpu/drm/i915/i915_drv.h | 2 + - drivers/gpu/drm/i915/i915_reg.h | 5 ++ - drivers/gpu/drm/i915/intel_pm.c | 110 ++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 117 insertions(+) - -diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h -index 915a3d0..04a7ceb 100644 ---- a/drivers/gpu/drm/i915/i915_drv.h -+++ b/drivers/gpu/drm/i915/i915_drv.h -@@ -1962,6 +1962,8 @@ struct drm_i915_private { - struct i915_suspend_saved_registers regfile; - struct vlv_s0ix_state vlv_s0ix_state; - -+ bool skl_sagv_enabled; -+ - struct { - /* - * Raw watermark latency values: -diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h -index ce14fe0..90d84b6 100644 ---- a/drivers/gpu/drm/i915/i915_reg.h -+++ b/drivers/gpu/drm/i915/i915_reg.h -@@ -7165,6 +7165,11 @@ enum { - #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 - #define DISPLAY_IPS_CONTROL 0x19 - #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A -+#define GEN9_PCODE_SAGV_CONTROL 0x21 -+#define GEN9_SAGV_DISABLE 0x0 -+#define GEN9_SAGV_LOW_FREQ 0x1 -+#define GEN9_SAGV_HIGH_FREQ 0x2 -+#define GEN9_SAGV_DYNAMIC_FREQ 0x3 - #define GEN6_PCODE_DATA _MMIO(0x138128) - #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 - #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 -diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c -index f4f3fcc..f9f55ca 100644 ---- a/drivers/gpu/drm/i915/intel_pm.c -+++ b/drivers/gpu/drm/i915/intel_pm.c -@@ -2876,6 +2876,109 @@ skl_wm_plane_id(const struct intel_plane *plane) - } - - static void -+skl_sagv_get_hw_state(struct drm_i915_private *dev_priv) -+{ -+ u32 temp; -+ int ret; -+ -+ if (IS_BROXTON(dev_priv)) -+ return; -+ -+ mutex_lock(&dev_priv->rps.hw_lock); -+ ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL, &temp); -+ mutex_unlock(&dev_priv->rps.hw_lock); -+ -+ if (!ret) { -+ dev_priv->skl_sagv_enabled = !!(temp & GEN9_SAGV_DYNAMIC_FREQ); -+ } else { -+ /* -+ * If for some reason we can't access the SAGV state, follow -+ * the bspec and assume it's enabled -+ */ -+ DRM_ERROR("Failed to get SAGV state, assuming enabled\n"); -+ dev_priv->skl_sagv_enabled = true; -+ } -+} -+ -+/* -+ * SAGV dynamically adjusts the system agent voltage and clock frequencies -+ * depending on power and performance requirements. The display engine access -+ * to system memory is blocked during the adjustment time. Having this enabled -+ * in multi-pipe configurations can cause issues (such as underruns causing -+ * full system hangs), and the bspec also suggests that software disable it -+ * when more then one pipe is enabled. -+ */ -+static int -+skl_enable_sagv(struct drm_i915_private *dev_priv) -+{ -+ int ret; -+ -+ if (IS_BROXTON(dev_priv)) -+ return 0; -+ if (dev_priv->skl_sagv_enabled) -+ return 0; -+ -+ mutex_lock(&dev_priv->rps.hw_lock); -+ DRM_DEBUG_KMS("Enabling the SAGV\n"); -+ -+ ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, -+ GEN9_SAGV_DYNAMIC_FREQ); -+ if (!ret) -+ dev_priv->skl_sagv_enabled = true; -+ else -+ DRM_ERROR("Failed to enable the SAGV\n"); -+ -+ /* We don't need to wait for SAGV when enabling */ -+ mutex_unlock(&dev_priv->rps.hw_lock); -+ return ret; -+} -+ -+static int -+skl_disable_sagv(struct drm_i915_private *dev_priv) -+{ -+ int ret = 0; -+ unsigned long timeout; -+ u32 temp; -+ -+ if (IS_BROXTON(dev_priv)) -+ return 0; -+ if (!dev_priv->skl_sagv_enabled) -+ return 0; -+ -+ mutex_lock(&dev_priv->rps.hw_lock); -+ DRM_DEBUG_KMS("Disabling the SAGV\n"); -+ -+ /* bspec says to keep retrying for at least 1 ms */ -+ timeout = jiffies + msecs_to_jiffies(1); -+ do { -+ ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, -+ GEN9_SAGV_DISABLE); -+ if (ret) { -+ DRM_ERROR("Failed to disable the SAGV\n"); -+ goto out; -+ } -+ -+ ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL, -+ &temp); -+ if (ret) { -+ DRM_ERROR("Failed to check the status of the SAGV\n"); -+ goto out; -+ } -+ } while (!(temp & 0x1) && jiffies < timeout); -+ -+ if (temp & 0x1) { -+ dev_priv->skl_sagv_enabled = false; -+ } else { -+ ret = -1; -+ DRM_ERROR("Request to disable SAGV timed out\n"); -+ } -+ -+out: -+ mutex_unlock(&dev_priv->rps.hw_lock); -+ return ret; -+} -+ -+static void - skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, - const struct intel_crtc_state *cstate, - struct skl_ddb_entry *alloc, /* out */ -@@ -3686,6 +3789,11 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc; - -+ if (dev_priv->active_crtcs == 1) -+ skl_enable_sagv(dev_priv); -+ else -+ skl_disable_sagv(dev_priv); -+ - for_each_intel_crtc(dev, crtc) { - int i, level, max_level = ilk_wm_max_level(dev); - enum pipe pipe = crtc->pipe; -@@ -4154,6 +4262,8 @@ static void skl_pipe_wm_active_state(uint32_t val, - PLANE_WM_LINES_MASK; - } - } -+ -+ skl_sagv_get_hw_state(dev_priv); - } - - static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) --- -2.9.2 - diff --git a/kernel.spec b/kernel.spec index 375e287..95fbc58 100644 --- a/kernel.spec +++ b/kernel.spec @@ -603,8 +603,7 @@ Patch665: netfilter-x_tables-deal-with-bogus-nextoffset-values.patch Patch835: 0001-Work-around-for-addition-of-metag-def-but-not-reloca.patch # https://lists.fedoraproject.org/archives/list/kernel@lists.fedoraproject.org/message/A4YCP7OGMX6JLFT5V44H57GOMAQLC3M4/ -Patch838: drm-i915-skl-Add-support-for-the-SAGV-fix-underrun-hangs.patch -Patch839: Revert-ALSA-hda-remove-controller-dependency-on-i915.patch +Patch839: drm-i915-Acquire-audio-powerwell-for-HD-Audio-regist.patch #CVE-2016-5412 rhbz 1349916 1361040 Patch842: kvm-ppc-Book3S-HV-Pull-out-TM-state-save.patch @@ -2144,6 +2143,10 @@ fi # # %changelog +* Tue Aug 2 2016 Hans de Goede +- Sync skylake hdaudio __unclaimed_reg WARN_ON fix with latest upstream version +- Drop drm-i915-skl-Add-support-for-the-SAGV-fix-underrun-hangs.patch for now + * Tue Aug 02 2016 Laura Abbott - 4.8.0-0.rc0.git4.1 - Linux v4.7-10753-g731c7d3